Patents by Inventor Gunther Lippert
Gunther Lippert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10347723Abstract: A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; forming a first graphene material on a first side of the silicon carbide wafer; bonding the first side of the silicon carbide wafer with the first graphene material to the carrier wafer; and splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting.Type: GrantFiled: November 13, 2018Date of Patent: July 9, 2019Assignee: Infineon Technologies AGInventors: Guenther Ruhl, Gunther Lippert, Hans-Joachim Schulze, Thomas Zimmer
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Publication number: 20190081143Abstract: A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; forming a first graphene material on a first side of the silicon carbide wafer; bonding the first side of the silicon carbide wafer with the first graphene material to the carrier wafer; and splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Guenther Ruhl, Gunther Lippert, Hans-Joachim Schulze, Thomas Zimmer
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Patent number: 10134848Abstract: A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer.Type: GrantFiled: March 21, 2017Date of Patent: November 20, 2018Assignee: Infineon Technologies AGInventors: Guenther Ruhl, Hans-Joachim Schulze, Thomas Zimmer, Gunther Lippert
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Publication number: 20170278930Abstract: A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer.Type: ApplicationFiled: March 21, 2017Publication date: September 28, 2017Inventors: Guenther Ruhl, Hans-Joachim Schulze, Thomas Zimmer, Gunther Lippert
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Patent number: 9590045Abstract: A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.Type: GrantFiled: May 23, 2014Date of Patent: March 7, 2017Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ—INSTITUT FUR INNOVATIVE MIKROELEKTRONIKInventors: Andre Wolff, Wolfgang Mehr, Grzegorz Lupina, Jaroslaw Dabrowski, Gunther Lippert, Mindaugas Lukosius, Chafik Meliani, Christian Wenger
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Publication number: 20160104778Abstract: A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.Type: ApplicationFiled: May 23, 2014Publication date: April 14, 2016Inventors: Andre Wolff, Wolfgang Mehr, Grzegorz Lupina, Jaroslaw Dabrowski, Gunther Lippert, Mindaugas Lukosius, Chafik Meliani, Christian Wenger
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Patent number: 9040956Abstract: A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer.Type: GrantFiled: December 11, 2009Date of Patent: May 26, 2015Assignee: IHP GmbH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIKInventors: Wolfgang Mehr, Gunther Lippert
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Patent number: 8957404Abstract: A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.Type: GrantFiled: December 20, 2012Date of Patent: February 17, 2015Assignee: IHP GmbH—Innovations for High Performance MicroelectronicsInventors: Wolfgang Mehr, Jaroslaw Dabrowski, Max Lemme, Gunther Lippert, Grzegorz Lupina, Johann Christoph Scheytt
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Patent number: 8778782Abstract: A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.Type: GrantFiled: November 29, 2011Date of Patent: July 15, 2014Assignee: IHP GmbH—Innovations for High Performance MicroelectronicsInventors: Gunther Lippert, Jaroslaw Dabrowski, Grzegorz Lupina, Olaf Seifarth
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Publication number: 20140027715Abstract: A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.Type: ApplicationFiled: December 20, 2012Publication date: January 30, 2014Applicant: IHP GmbH - Innovations for High Performance MicroelectronicsInventors: Wolfgang Mehr, Jaroslaw Dabrowski, Max Lemme, Gunther Lippert, Grzegorz Lupina, Johann Christoph Scheytt
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Patent number: 8227888Abstract: A semiconductor component including a first integrated circuit in a substrate which is adapted to produce electrical signals with a high-frequency signal component, wherein the substrate is such that the high-frequency signal component can propagate on a substrate surface and/or in the substrate interior, a second integrated circuit in the same substrate which is such that its function can be compromised by high-frequency signals, and a countersignal circuit in the same substrate which is adapted to deliver an electrical countersignal which at least at a selected location of the substrate surface and/or the substrate interior attenuates or eliminates the high-frequency electrical signal component emanating from the first integrated circuit, wherein the countersignal circuit includes a receiver which is adapted to produce an electrical signal dependent on the instantaneous field strength of the high-frequency signal component, and a shielding transistor provided in the substrate and having a control electrodeType: GrantFiled: April 8, 2005Date of Patent: July 24, 2012Assignee: IHP GmbH—Innovations for High Performance MicroelectronicsInventors: Gunther Lippert, Gerald Lippert
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Publication number: 20120132885Abstract: A method for fabricating an electronic component, comprising providing a substrate; and depositing a graphene layer; wherein the substrate is either provided with a van-der-Waals functional layer or a van-der-Waals functional layer is deposited on the substrate before depositing the graphene layer; a surface step contour is formed; and growth of the graphene layer is seeded at the step contour.Type: ApplicationFiled: November 29, 2011Publication date: May 31, 2012Applicants: innovative MikroelektrInventors: Gunther LIPPERT, Jaroslaw Dabrowski, Grzegorz Lupina, Olaf Seifarth
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Publication number: 20120032150Abstract: Semiconductor component comprising: a silicon containing layer (1), at least one graphene layer (3, 3?, 3?, 3?41 ), and a functional layer (2, 2?, 2?, 2??) between the silicon containing layer (1) and the graphene layer (3, 3?, 3?, 3??), wherein the at least one graphene layer (3?, 3?, 3??) is deposited directly on the functional layer (2, 2?, 2?, 2??) to form a layer system (6, 6?, 6?, 6??) with the functional layer (2, 2?, 2?, 2??) , and the functional layer (2, 2?, 2?, 2??) includes at least one dielectric material having a dielectric constant k in a range between K=3 to K=400, and a conductance of the functional layer (2, 2?, 2?, 2??) in the layer system (6, 6?, 6?, 6??) is below a conductance of the graphene layer (3, 3?, 3?, 3??).Type: ApplicationFiled: June 29, 2011Publication date: February 9, 2012Inventors: Gunther Lippert, Grzegorz Lupina, Olaf Seifarth, Marvin Zöllner, Hans-Joachim Thieme
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Publication number: 20110309335Abstract: A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer.Type: ApplicationFiled: December 11, 2009Publication date: December 22, 2011Inventors: Wolfgang Mehr, Gunther Lippert
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Publication number: 20110133303Abstract: A semiconductor component including a first integrated circuit in a substrate which is adapted to produce electrical signals with a high-frequency signal component, wherein the substrate is such that the high-frequency signal component can propagate on a substrate surface and/or in the substrate interior, a second integrated circuit in the same substrate which is such that its function can be compromised by high-frequency signals, and a countersignal circuit in the same substrate which is adapted to deliver an electrical countersignal which at least at a selected location of the substrate surface and/or the substrate interior attenuates or eliminates the high-frequency electrical signal component emanating from the first integrated circuit, wherein the countersignal circuit includes a receiver which is adapted to produce an electrical signal dependent on the instantaneous field strength of the high-frequency signal component, and a shielding transistor provided in the substrate and having a control electrodeType: ApplicationFiled: April 8, 2005Publication date: June 9, 2011Inventors: Gunther Lippert, Gerald Lippert
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Publication number: 20060286734Abstract: Disclosed is an electronic device with a layer succession of the metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) kind. The insulator layer contains or consists of praseodymium titanate. A metal layer or both metal layers contain titanium nitride (TiN), tantalum nitride (TaN) or ruthenium oxide (RuO2) or consist of one of those materials. MIM capacitors for mixed signal and HF applications comprising titanium nitride electrodes and an SiO2/Pr2Ti2O7 layer stack as the dielectric exhibit a high capacitance density of 8 fF/?m2 at the very low VCC of ?40 ppm/V2. The guaranteed operating voltage extrapolated to 10 years is 6 V.Type: ApplicationFiled: June 14, 2006Publication date: December 21, 2006Inventors: Hans-Joachim Mussig, Gunther Lippert, Christian Wenger
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Patent number: 7019341Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.Type: GrantFiled: August 30, 2002Date of Patent: March 28, 2006Assignee: IHP GmbH - Innovations for High Performance Microelectronics/Instut fur Innovative MikroelektronikInventors: Gunther Lippert, Hans-Jörg Osten, Bernd Heinemann
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Patent number: 6800881Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.Type: GrantFiled: August 30, 2002Date of Patent: October 5, 2004Assignee: IHP GmbH-Innovations for High Performance Microelectronics/Institut fur Innovative MikroelektronikInventors: Gunther Lippert, Hans-Jörg Osten, Bernd Heinemann
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Patent number: 6750484Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, carbon is incorporated in the base layer and in the collector layer and/or emitter layer.Type: GrantFiled: August 30, 2002Date of Patent: June 15, 2004Assignee: Nokia CorporationInventors: Gunther Lippert, Hans-Jörg Osten, Bernd Heinemann
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Publication number: 20030071278Abstract: The invention relates to a silicon germanium hetero bipolar transistor and a method of fabricating the epitaxial individual layers of a silicon germanium hetero bipolar transistor.Type: ApplicationFiled: August 30, 2002Publication date: April 17, 2003Inventors: Gunther Lippert, Hans-Jorg Osten, Bernd Heinemann