Abstract: A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.

Abstract: Each of the check bits of an ECC codeword is generated in parallel in a byte serial sequence to permit structuring of the ECC device so that it has general application. For this purpose a byte wide check bit generator is provided for each of the check bits. These check bit generators contain generalized gating logic controlled by stored data that is capable of passing any combination of the bits making up the byte. As each byte enters such a check bit generator, the data controlling the gating logic is changed to generate a partial sum of the check bit using only those data bits from that data byte designated by the H matrix on the ECC. The partial check bits are then accumulated modulo 2 to generate the check bit to be stored with the data bits.