Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10?4 mg/cm2 to 0.1 mg/cm2.

Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10?4 mg/cm2 to 0.1 mg/cm2.

Abstract: A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping.

Abstract: A sensor arrangement according to an embodiment comprises a transmitter to be arranged inside a battery cell and to transmit a signal based on at least one sensed operational parameter of the battery cell wirelessly.

Abstract: A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping.

Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10?4 mg/cm2 to 0.1 mg/cm2.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A lithography apparatus includes a first optical system configured to irradiate a mask with a non-telecentric illumination and a second optical system configured to guide radiation reflected off or transmitted through the mask to a substrate. The mask includes an absorber structure arranged over a non-absorbing surface, wherein the absorber structure includes sidewalls extending in a first direction intersecting a main plane of incidence of the non-telecentric illumination. The sidewall angle of the sidewalls may be at most equal to 90° minus the angle of incidence of the non-telecentric illumination and at least equal to 90° minus the sum of the angle of incidence and a half acceptance angle of the second optical system.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A process enables plasma etching of materials that do not contain silicon. The process is particularly suitable for the side wall passivation of chromium layers in masks for fabricating semiconductor components. The plasma contains oxygen and/or nitrogen, and at least one silicon-donating compound is introduced into the plasma. This allows efficient passivation of side walls.

Abstract: A method for compensating for scatter/reflection effects in particle beam lithography includes the following steps: providing at least one layer of a material that is sensitive to particle beams, using at least one particle beam to write predetermined patterns in a limited area of the material that is sensitive to particle beams, and using at least one particle beam to write at least one frame, which surrounds the limited area, into the material that is sensitive to particle beams so that variations in the background dose within the limited area are less than 30% of the maximum background dose within the limited area. This provides the advantage that a considerably more homogeneous background dose and hence considerably less variation in the CD measure, can be produced within the area that is written to by the particle beam, in a simple and cost-effective manner.

Abstract: The present invention provides a production method for a halftone phase mask which has an SiO2 substrate, an overlying refractory metal SixNy phase shifter layer (2) and an overlying chromium oxide or chromium mask layer (3), having the following steps: provision of a mask (4) on the chromium oxide or chromium mask layer (3); etching of the chromium oxide or chromium mask layer (3) for the purpose of forming a hard mask from the chromium oxide or chromium mask layer (3) in a first etching step; selective etching of the refractory metal SixNy phase shifter layer (2) using the hard mask in a plasma with a chlorine-containing and/or hydrogen-chloride-containing main gas in a second etching step with a predetermined cathode power of at least 20 W.

Abstract: A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH3F and O2. A high cathode power is used for the etching. The method has a very high selectivity between the substrate and the phase shift layer, so that half-tone phase masks with a high imaging quality can be produced.

Abstract: The present invention provides a production method for a halftone phase mask which has an SiO2 substrate, an overlying refractory metal SixNy phase shifter layer (2) and an overlying chromium oxide or chromium mask layer (3), having the following steps: provision of a mask (4) on the chromium oxide or chromium mask layer (3); etching of the chromium oxide or chromium mask layer (3) for the purpose of forming a hard mask from the chromium oxide or chromium mask layer (3) in a first etching step; selective etching of the refractory metal SixNy phase shifter layer (2) using the hard mask in a plasma with a chlorine-containing and/or hydrogen-chloride-containing main gas in a second etching step with a predetermined cathode power of at least 20 W.

Abstract: A method for compensating for scatter/reflection effects in particle beam lithography includes the following steps: providing at least one layer of a material that is sensitive to particle beams, using at least one particle beam to write predetermined patterns in a limited area of the material that is sensitive to particle beams, and using at least one particle beam to write at least one frame, which surrounds the limited area, into the material that is sensitive to particle beams so that variations in the background dose within the limited area are less than 30% of the maximum background dose within the limited area. This provides the advantage that a considerably more homogeneous background dose and hence considerably less variation in the CD measure, can be produced within the area that is written to by the particle beam, in a simple and cost-effective manner.

Abstract: A process enables plasma etching of materials that do not contain silicon. The process is particularly suitable for the side wall passivation of chromium layers in masks for fabricating semiconductor components. The plasma contains oxygen and/or nitrogen, and at least one silicon-donating compound is introduced into the plasma. This allows efficient passivation of side walls.

Abstract: A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH3F and O2. A high cathode power is used for the etching. The method has a very high selectivity between the substrate and the phase shift layer, so that half-tone phase masks with a high imaging quality can be produced.

Abstract: A method and a device are proposed for delacquering a mask substrate, in the case of which, in particular, the edge zone of a photomask is delacquered. During the mask production, the mask substrate is coated over its entire surface with a layer of photoresist by the production process. The side edges can also be coated with resist in this case. During later handling of the mask substrates, very small resist particles can come loose, for example owing to handling tools such as mask pincers, and lead through deposits on the emulsion side to defects in the layout of the mask substrates such that the photomask can then no longer be used in practice. This fault can be avoided by delacquering the edge zone with the aid of a chemical etching reaction, in particular by using an ozone-containing gas.