Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.

Abstract: A nanoporous (NP) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk. The nanoporous material of the nanoporous layer may be a metal oxide, metal chalcogenide, or a combination thereof. Further, the memory may lack any additional components. Further, the memory may be free from requiring an electroformation process to allow switching between ON/OFF states.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Abstract: A nanoporous (NP) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk. The nanoporous material of the nanoporous layer may be a metal oxide, metal chalcogenide, or a combination thereof. Further, the memory may lack any additional components. Further, the memory may be free from requiring an electroformation process to allow switching between ON/OFF states.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.