Patents by Inventor Gunvant T. Patel
Gunvant T. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7518392Abstract: Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide high speed pin continuity and pin-to-pin short tester circuits. Such circuits include a threshold driver, a test driver, and a comparator. An input of the threshold driver is electrically coupled to a voltage threshold, and an output of the threshold driver is electrically coupled to a test pin node via a current limiting resistor. An input of the test driver is electrically coupled to a drive data input, and an output of the test driver is electrically coupled to the test pin node. One input of the comparator is electrically coupled to the test pin node, and the other input of the comparator is electrically coupled to a threshold comparator input.Type: GrantFiled: August 2, 2006Date of Patent: April 14, 2009Assignee: Texas Instruments IncorporatedInventors: Gunvant T. Patel, Trevor J. Tarsi, Yun-Fu Wang, Anthony J. Lendino
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Patent number: 7424654Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.Type: GrantFiled: August 23, 2005Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Dennis Harold Burke, Jr., Michael Lee Martel, Gunvant T. Patel
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Publication number: 20080089401Abstract: One embodiment of the invention includes a method for testing the performance of a Global System for Mobile Communications (GSM) transmitter. The output of the GSM transmitter is converted to a digital signal. A power spectrum is estimated for the GSM transmitter according to the digital signal via a modified periodogram algorithm. A phase trajectory of the digital signal is determined, and an ideal phase signal is determined from the determined phase trajectory. A phase trajectory error is calculated from the determined phase trajectory and the determined ideal phase signal. A tested device may be considered compliant if the abovementioned phase error and spectral mask meet specific defined criteria, and fails the test if either of these does not meet the predefined limits. The present invention is targeted at reducing the test time and test equipment traditionally associated with the implementation of these tests.Type: ApplicationFiled: September 25, 2007Publication date: April 17, 2008Inventors: Pao-Jen Lai, Khurram Waheed, Oren Eliezer, Gunvant T. Patel, Oscar Barraza
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Publication number: 20080030217Abstract: Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide high speed pin continuity and pin-to-pin short tester circuits. Such circuits include a threshold driver, a test driver, and a comparator. An input of the threshold driver is electrically coupled to a voltage threshold, and an output of the threshold driver is electrically coupled to a test pin node via a current limiting resistor. An input of the test driver is electrically coupled to a drive data input, and an output of the test driver is electrically coupled to the test pin node. One input of the comparator is electrically coupled to the test pin node, and the other input of the comparator is electrically coupled to a threshold comparator input.Type: ApplicationFiled: August 2, 2006Publication date: February 7, 2008Applicant: Texas Instruments IncorporatedInventors: Gunvant T. Patel, Trevor J. Tarsi, Yung-Fu Wang, Anthony J. Lendino
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Patent number: 6941232Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.Type: GrantFiled: February 14, 2003Date of Patent: September 6, 2005Assignee: Texas Instruments IncorporatedInventors: Dennis Harold Burke, Jr., Michael Lee Martel, Gunvant T. Patel
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Patent number: 6919727Abstract: Disclosed is a method of measuring the time signal of an electronic device including steps for measuring a true signal and an inverted signal. The measured true path signal and inverted path signal are combined to reduce measurement error and provide an accurate measurement of the time signal of the device under test. Also disclosed is an interface for use between a device-under-test and test equipment. The interface includes means for alternately switching a time signal from the device-under-test to provide a true signal path and an inverted signal path for measurement. A system embodiment of the invention is also disclosed in which an interface and measuring means are used to alternately measure and combine a true signal and an inverted signal to provide an accurate time measurement result.Type: GrantFiled: September 26, 2002Date of Patent: July 19, 2005Assignee: Texas Instruments IncorporatedInventors: Gunvant T. Patel, Nicholas Flores
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Publication number: 20040162682Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.Type: ApplicationFiled: February 14, 2003Publication date: August 19, 2004Applicant: Texas Instruments IncorporatedInventors: Dennis Harold Burke, Michael Lee Martel, Gunvant T. Patel
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Publication number: 20040061507Abstract: Disclosed is a method of measuring the time signal of an electronic device including steps for measuring a true signal and an inverted signal. The measured true path signal and inverted path signal are combined to reduce measurement error and provide an accurate measurement of the time signal of the device under test. Also disclosed is an interface for use between a device-under-test and test equipment. The interface includes means for alternately switching a time signal from the device-under-test to provide a true signal path and an inverted signal path for measurement. A system embodiment of the invention is also disclosed in which an interface and measuring means are used to alternately measure and combine a true signal and an inverted signal to provide an accurate time measurement result.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Inventors: Gunvant T. Patel, Nicholas Flores