Abstract: A pixel circuit may include a light-emitting element, a driving transistor which applies a driving current to the light-emitting element, a storage capacitor connected to a control electrode of the driving transistor, a data voltage-applying transistor which applies a data voltage to the storage capacitor, an emission transistor which connects the driving transistor to the light-emitting element in response to an emission signal, and a bias capacitor disposed between a first electrode of the driving transistor and a control electrode of the emission transistor.

Abstract: A pixel includes a first capacitor electrically connected between a first node and a second node, a second capacitor electrically connected between a first driving voltage line providing a first driving voltage and the first node, a light emitting diode including a first electrode and a second electrode electrically connected with a second driving voltage line providing a second driving voltage, first to fourth transistors, each including a first electrode, a second electrode, and a gate.

Abstract: A display apparatus includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first driving transistor and a first storage capacitor having a first lower storage electrode connected to a gate of the first driving transistor and a first upper storage electrode overlapping the first lower storage electrode. The second pixel circuit includes a second driving transistor and a second storage capacitor including a second lower storage electrode connected to a gate of the second driving transistor and a second upper storage electrode overlapping the second lower storage electrode. A second overlapping area of the second lower storage electrode and the second upper storage electrode is about twice to about four times a first overlapping area of the first lower storage electrode and the first upper storage electrode.

Abstract: A pixel circuit may include a light-emitting element, a driving transistor which applies a driving current to the light-emitting element, a storage capacitor connected to a control electrode of the driving transistor, a data voltage-applying transistor which applies a data voltage to the storage capacitor, an emission transistor which connects the driving transistor to the light-emitting element in response to an emission signal, and a bias capacitor disposed between a first electrode of the driving transistor and a control electrode of the emission transistor.

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

Abstract: A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

Abstract: A method of detecting a pixel defect for detecting a defect of a pixel including first to fourth transistors, connected to a data line, and receiving a scan signal and an initialization control signal includes turning on the first through fourth transistors by changing the scan signal and the initialization control signal to have a turn-on voltage level in an inspection period, detecting an inspecting current flowing in a path corresponding to the first through fourth transistors using a current detector that is connected to the data line, determining that a threshold voltage of the second transistor is within a normal range when the inspecting current is within a reference range, and determining that the threshold voltage of the second transistor is out of the normal range when the inspecting current is out of the reference range.

Abstract: A method of detecting a pixel defect for detecting a defect of a pixel including first to fourth transistors, connected to a data line, and receiving a scan signal and an initialization control signal includes turning on the first through fourth transistors by changing the scan signal and the initialization control signal to have a turn-on voltage level in an inspection period, detecting an inspecting current flowing in a path corresponding to the first through fourth transistors using a current detector that is connected to the data line, determining that a threshold voltage of the second transistor is within a normal range when the inspecting current is within a reference range, and determining that the threshold voltage of the second transistor is out of the normal range when the inspecting current is out of the reference range.

Abstract: A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode.

Abstract: A display apparatus includes a voltage generator which generates an initial controlling signal which comprises a high voltage, a middle voltage and a low voltage, where the initial controlling signal swings from the middle voltage to the low voltage after a plurality of gate signals is simultaneously dropped from a high voltage to a low voltage thereof.

Abstract: A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

Abstract: A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

Abstract: A display apparatus includes a voltage generator which generates an initial controlling signal which comprises a high voltage, a middle voltage and a low voltage, where the initial controlling signal swings from the middle voltage to the low voltage after a plurality of gate signals is simultaneously dropped from a high voltage to a low voltage thereof.

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.

Abstract: A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

Abstract: A liquid crystal display which enhances an aperture ratio and stabilizes a storage voltage includes a first substrate, a second substrate opposing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate, a first transistor connected to the gate line, the data line, and the first sub-pixel electrode, and a second transistor connected to the gate line, the data line, and the second sub-pixel electrode and including a source electrode, a drain electrode and at least one floating electrode between the source electrode and the drain electrode.

Abstract: A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode.

Abstract: An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.

Abstract: A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.