Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: A sampling phase calibrating method, comprising: transmitting a second command signal from a storage device controller, to read content in a storage device; transmitting a first command signal and a third data signal with a third sampling phase from the storage device controller to the storage device, according to the content; and determining if data transmitting from the storage device controller to the storage device has error, according to responding information that the storage device responds to the storage device controller corresponding to the first command signal and the third data signal, to determine if the third sampling phase is suitable; wherein the second command signal is transmitted via a second clock, the first command signal is transmitted via a first clock, where the second clock is slower than the first clock.