Abstract: Disclosed are compounds of Formula (I), Formula (II), or a salt thereof: Formula (I) Formula (II) which compounds have properties for inhibiting Nav 1.7 ion channels found in peripheral and sympathetic neurons. Also described are pharmaceutical formulations comprising the compounds of Formula (I), Formula (II) or their salts, and methods of treating pain disorders, cough, and itch using the same.

Abstract: The present invention provides an intelligent resilience urban-rural evaluation system and a method thereof. The system includes: a data acquisition module, a data processing module, a model building module and an evaluation calculation module. Through the study of influence of earthquake motion time history on reliability and safety of building structures, reliability evaluation and health monitoring of complex building structure systems are realized by using super-computing and storage capabilities of cloud computing.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: A physical container (e.g., a battery) may be filled up (charged) or emptied (discharged) with energy commensurate with requirements to post a particular amount of collateral. The disclosure provides computing systems and methods for processing data using a novel combination of wavelet techniques and rolling techniques to more efficiently detect seasonality in particular products (e.g., energy products) to more accurately model and determine collateral/margin requirements. A clearinghouse computing device may be configured to generate a margin requirement for a portfolio of products and may include a processor to process instructions that cause the clearinghouse computing device to perform wavelet decomposition and rolling methods on a historical database of records.

Abstract: A physical container (e.g., a battery) may be filled up (charged) or emptied (discharged) with energy commensurate with requirements to post a particular amount of collateral. The disclosure provides computing systems and methods for processing data using a novel combination of wavelet techniques and rolling techniques to more efficiently detect seasonality in particular products (e.g., energy products) to more accurately model and determine collateral/margin requirements. A clearinghouse computing device may be configured to generate a margin requirement for a portfolio of products and may include a processor to process instructions that cause the clearinghouse computing device to perform wavelet decomposition and rolling methods on a historical database of records.

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.

Abstract: A system may be configured to generate an estimate of value at risk and may include a processor to process instructions that cause the system to generate a rolling time series of value data having a plurality of dimensions, perform a transformation of the time series, perform variance scaling and correlation scaling on transformed time series, reverse transform the results of the scaling, and estimate of a value-at-risk for the value data.

Abstract: A method for processing scanning electron microscope specimen is provided. The method comprises: providing a specimen to be observed; providing a carbon nanotube array comprising a plurality of carbon nanotubes; and pulling a carbon nanotube film from the carbon nanotube array, and laying the carbon nanotube film on a surface of the specimen, wherein the carbon nanotube film comprising a plurality of through holes.

Abstract: Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.

Abstract: A system may be configured to generate an estimate of value at risk and may include a processor to process instructions that cause the system to generate a rolling time series of value data having a plurality of dimensions, perform rotation transform of the time series, perform variance scaling and correlation scaling on transformed time series, reverse transform the results of the scaling, and estimate of a value-at-risk for the value data.

Abstract: The present disclosure relates to a cover plate assembly for a lithium ion battery and a lithium ion battery. The cover plate assembly includes a cover plate body, provided at a middle portion thereof with a through hole which extends to form a tube body, and the tube body protrudes from at least one surface of the cover plate body; a pressure relief portion, wherein the pressure relief portion is located in the tube body and is in sealed communication with the tube body, the pressure relief portion is ring-shaped and is configured to crack and split from the cover plate body in response to deformation of the cover plate body; and a central conductor, embraced by the pressure relief portion and runs through the pressure relief portion along the axial direction. The cover plate assembly features excellent safety performance and small space occupation.

Abstract: A pyridine pyrrole ruthenium coordination complex, a preparation method therefor and use thereof as a catalyst for electrocatalyzing ammonia oxidation to prepare hydrazine is provided. The pyridine pyrrole ruthenium coordination complex takes high-activity metal ruthenium as a central metal ion and compounds containing pyridine pyrrole with electron withdrawing/donating capability as ligands, and thus has relatively high catalytic activity for ammonia oxidation. High conversion rate and highly selective conversion of ammonia can be realized by applying the pyridine pyrrole ruthenium coordination complex to electrocatalytic ammonia oxidation in an organic solvent, with major products including H2, N2, N2H4.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: An device for measuring electron beam comprises a Faraday cup comprising an opening; a porous carbon material layer located on a surface of the Faraday cup and suspended at the opening; and an electricity meter electrically connected to the porous carbon material layer. A length of a suspended portion of the porous carbon material layer is greater than or equal to a maximum diameter of an electron beam to be measured. A diameter or a width of the porous carbon material layer is smaller than a minimum diameter of a cross section of the electron beam to be measured. The porous carbon material layer comprises a plurality of carbon material particles, and a plurality of micro gaps exist between the plurality of carbon material particles. A method for measuring an electron beam using the device for measuring electron beam is also provided.

Abstract: A method for preparing an amorphous silicon powder for an anode material of a lithium-ion battery is disclosed. The amorphous silicon powder is prepared by reducing an oxide of silicon, wherein an X-ray diffraction peak of an amorphous silicon material is weak, and the amorphous silicon material is of an amorphous structure. A structural formula of the oxide of silicon is SiOx, wherein 0<x?2. The reduction refers to vapor phase reduction, a vapor phase reduction atmosphere is a mixed gas of hydrogen and carbon monoxide, a reduction temperature ranges from 100° C. to 700° C., and a reduction time ranges from 2 h to 72 h.

Abstract: A docking station is for accommodating a tablet computer device. In an embodiment, the docking station includes a housing, and an interface apparatus for connecting the tablet computer device to the housing. The housing is configured to accommodate the interface apparatus in a form-fit manner. The interface apparatus is configured such that the tablet computer device is dockable in a form-fit manner to the interface apparatus upon the interface apparatus being accommodated in a form-fit manner in the housing.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.