Patents by Inventor Guo Cheng Chen

Guo Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 5099408
    Abstract: A system is provided for controlling a PWM inverter having three main circuit arms in which free-wheel diodes are connected in parallel to positive and negative side switching elements. The inverter takes three phase alternating current from an intermediate portion of the arms on the basis of a voltage supply of a direct current and an ON and OFF operation of the switching elements. The control system includes a circuit for detecting a zero-crossing point of the three phase alternating current. A wave generating circuit generates a PWM wave at every main circuit arm, which changes the level thereof corresponding to ON and OFF operation of the switching elements and is inverted to each other in the positive and negative sides. An on-delay circuit delays a level change timing from ON to OFF of the PWM wave for a short circuit preventing duration.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: March 24, 1992
    Assignee: Kasuga Denki Kabushiki Kaisha
    Inventors: Guo Cheng Chen, Yukio Kawa