Patents by Inventor Guo Feng Lian

Guo Feng Lian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9520380
    Abstract: A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 13, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian
  • Publication number: 20160079203
    Abstract: A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian
  • Patent number: 9245861
    Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 26, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian, Hong Xia Fu, Yu Ping Gong
  • Publication number: 20140315350
    Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian, Hong Xia Fu, Yu Ping Gong
  • Patent number: 8703545
    Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Zhiqiang Niu, Ming-Chen Lu, Yan Xun Xue, Yan Huo, Hua Pan, Guo Feng Lian, Jun Lu
  • Publication number: 20130221507
    Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventors: Zhiqiang Niu, Ming-Chen Lu, Yan Xun Xue, Yan Huo, Hua Pan, Guo Feng Lian, Jun Lu