Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.

Abstract: An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.

Abstract: A method includes fabricating a first-type active-region semiconductor, depositing a layer of dielectric material covering the first-type active-region semiconductor structure, and fabricating a second-type active-region semiconductor structure atop the layer of dielectric material. The method includes forming a front-side power rail and a front-side signal line extending in the first direction in a front-side metal layer overlying a first insulating material that covers the first-type active-region semiconductor. The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure. The method includes forming a back-side metal layer on a backside of the substrate, and forming a back-side power rail and a back-side signal line extending in the first direction in the back-side metal layer.

Abstract: A semiconductor cell structure includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail. Each of the first-type active zone and the second-type active zone is between a first alignment boundary and a second alignment boundary extending in a first direction which is perpendicular to a second direction. A first distance along the second direction between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance along the second direction between the long edge of the second power rail and the first alignment boundary of the second-type active zone by a predetermined distance.

Abstract: A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Abstract: A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

Abstract: An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.

Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

Abstract: A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.

Abstract: A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.