Patents by Inventor Guo-Liang ZHUANG

Guo-Liang ZHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237332
    Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 12218132
    Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20100201934
    Abstract: A display panel is provided, which includes a first substrate having a first surface, a second substrate having a second surface facing the first surface and having at least an opening portion extending downward from the second surface, wherein the opening portion occupies an area no greater than that occupied by a portion of the second surface other than the opening portion, a liquid crystal layer sandwiched between the first substrate and the second substrate, at least a first spacer disposed between the first substrate and the second substrate, and at least a second spacer disposed between the first substrate and the second substrate, wherein an end of the second spacer is within the opening portion.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 12, 2010
    Applicant: TPO Displays Corp.
    Inventors: Shang-Chin FAN, Guo-Liang ZHUANG, Mei-Wen LU, Sheng-Nan FAN, Dai-Liang TING