Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

Abstract: A method for performing access control between a host device and a memory device, an associated bridge device and a bridge controller thereof are provided, where the method is applicable to the bridge device for coupling the memory device to the host device. The method may include: receiving a first test command; returning failure information; receiving a request command; returning device-related information; receiving a second test command; returning pass information; receiving a capacity-related command; reporting a reported logical address (LA) count of the memory device and a reported sector size of the memory device; and performing bi-directional mapping between a memory device side LA format of a set of LAs at the memory device side corresponding to the memory device and a host device side LA format of a set of LAs at the host device side corresponding to the host device during access operation that the host device performs.

Abstract: The invention introduces an apparatus for accessing a memory card to at least include a host interface and a processing unit. The processing unit is arranged to operably inspect whether a logical block length utilized in a memory card inserted into a card reader can be supported by a host; and reply to the host with sense data that advises the host not to perform a subsequent write into the memory card through the host interface in response to a request sense command when the logical block length utilized in the memory card cannot be supported by the host.