Abstract: The present disclosure relates to a game interactive control method and apparatus, a storage medium and an electronic device, and relates to the technical field of computers. According to the method, by determining the game intention of the agent according to the game state information, and inputting the game state information, the game communication information and the game intention into the communication prediction model, the target communication content corresponding to the agent is obtained, and then the target communication content is outputted, so that the player character determines a game action to be executed by the agent based on the target communication content. This can not only improve the gaming activity when the real player is battling against the agent, but also enable the real player to know the game intention of the agent so as to cooperate with the agent and improve the gaming quality.

Abstract: Related to are a method and apparatus for game role interaction control, a storage medium, and an electronic device. In the method, a target communication period of an intelligent agent may be dynamically adjusted by the current signal communication information triggered by a game match and the current game state information of the game match, to adjust the frequency of the intelligent agent for sending communication messages in the game match. Therefore, in the case of active communication of real players, the intelligent agent can be prevented from frequently sending communication messages, resulting in a conflict with the communication messages of the real players, and the interference of excessive communication messages on the real players can also be prevented. Moreover, in the case of no communication of the real players, the communication willingness of the real players can be motivated, thereby ensuring a good battle atmosphere for the game match.

Abstract: A method, apparatus, electronic device and storage medium for combat control are provided. The method comprising: determining, according to current game status data and communication information of the target object, a communicated strategic intention of a target object, wherein the communicated strategic intention characterizes a combat target expressed by the communication information; determining, according to the game status data, an initial strategic intention of a virtual object in response to the game state data; determining, according to the initial strategic intention and the communicated strategic intention, the target strategic intention of the virtual object; determining a response action of the virtual object based on the target strategic intention, and controlling the virtual object to perform the response action.

Abstract: The present disclosure relates to the technical field of computers, and in particular to a game character control method and apparatus, a storage medium and an electronic device. In the method, game state information of a game match is adjusted according to game alignments to which an intelligent agent and a player character belong, so as to obtain target state information, a target game intention of the intelligent agent is determined according to the target state information, then a target operation of the intelligent agent in the game match is determined according to the target state information and the target game intention, and the target operation executed by the intelligent agent may be adjusted according to different game situations, so that the intelligent agent can flexibly adjust game actions to provide different playing methods in a human-computer battle.

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.