Patents by Inventor Guobin Yu

Guobin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562932
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 24, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Guobin Yu, Xiaoping Xu
  • Patent number: 10229926
    Abstract: A method for manufacturing a flash memory device includes providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer. The method also includes performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer, and forming an isolation region on side surfaces of the stack structure. The method can mitigate the problem of an undesirable increase in the threshold voltage with an increase in the integration density of the flash memory device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 12, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guobin Yu, Xiaoping Xu
  • Publication number: 20180277441
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 27, 2018
    Inventors: Guobin Yu, Xiaoping Xu
  • Publication number: 20180277557
    Abstract: A method for manufacturing a flash memory device includes providing a substrate structure including a substrate, an insulating layer on the substrate, and a stack structure including a charge storage layer, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a gate layer disposed sequentially from bottom to top on the insulating layer. The method also includes performing a selective nitriding process on the substrate structure to form a nitride layer exposed surfaces of the charge storage layer and the gate layer, and forming an isolation region on side surfaces of the stack structure. The method can mitigate the problem of an undesirable increase in the threshold voltage with an increase in the integration density of the flash memory device.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 27, 2018
    Inventors: GUOBIN YU, Xiaoping Xu
  • Patent number: 9613868
    Abstract: A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 4, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Guobin Yu
  • Publication number: 20160064379
    Abstract: A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventor: GUOBIN YU
  • Patent number: 9184291
    Abstract: A method for manufacturing a fin for a FinFET device includes providing a semiconductor substrate, forming a plurality of implanted regions in the semiconductor substrate, and epitaxially forming fins between two adjacent implanted regions. The method also includes forming an insulating structure between two adjacent fins.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 10, 2015
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Guobin Yu, Jing Lin
  • Publication number: 20150060961
    Abstract: A method for manufacturing a fin for a FinFET device includes providing a semiconductor substrate, forming a plurality of implanted regions in the semiconductor substrate, and epitaxially forming fins between two adjacent implanted regions. The method also includes forming an insulating structure between two adjacent fins.
    Type: Application
    Filed: February 25, 2014
    Publication date: March 5, 2015
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: GUOBIN YU, Jing Lin
  • Patent number: 8665938
    Abstract: A wireless transmission apparatus includes a service processing unit, a duplexer, a radio frequency receiving unit, a frequency synthesizer, and a controller. The controller controls, according to a reduced TR interval, the frequency synthesizer to adjust a frequency of a local oscillation signal which is output by the frequency synthesizer to the radio frequency receiving unit. The service processing unit continues to send a service signal as a self-checking signal, and a part of the self-checking signal leaks into the radio frequency receiving unit through the duplexer. After the radio frequency receiving unit mixes a received signal with the local oscillation signal, a frequency of the self-checking signal included in an output signal falls within a pass-band range of an intermediate frequency receiving unit, which ensures that the self-checking signal can be looped back to the service processing unit, thereby determines whether a fault occurs in its own transmission channel.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Guobin Yu, Hongyong Lin, Yicai Wang