Abstract: A computer program product for implementing a scan chain to test a semiconductor including one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions including: program instructions to obtain an initial structure of the scan chain, program instructions to determine, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency, program instructions to adjust the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency, and program instructions to determine a key subset of a fan-out scan register in the at least one scan register pair with backward dependency.

Abstract: A computer program product for implementing a scan chain to test a semiconductor including one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions including: program instructions to obtain an initial structure of the scan chain, program instructions to determine, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency, program instructions to adjust the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency, and program instructions to determine a key subset of a fan-out scan register in the at least one scan register pair with backward dependency.

Abstract: A method for implementing a scan chain to test a semiconductor including obtaining an initial structure of the scan chain, determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, a first scan register pair with backward dependency, adjusting a structure of the scan chain such that the first scan register pair with backward dependency becomes a scan register pair with forward dependency, when a fan-in scan register in the scan register pair with backward dependency belongs to the key subset of the fan-out scan register in the first scan register pair with backward dependency, and determining a key subset of a fan-out scan register in the first scan register pair with backward dependency, wherein when all fan-in scan registers in the key subset reflect a same logic value, an output logic value of a function module connected to the fan-out scan register is fixed.

Abstract: A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Abstract: A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

Abstract: A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.