Abstract: A fuel cell cathode catalyst layer structure for enhancing the durability of a catalyst is provided. The cathode catalyst layer structure includes a first catalyst portion, a second catalyst portion, and a third catalyst portion that are arranged in sequence from an area close to a diffusion layer to an area close to a proton exchange membrane (PEM); a pure platinum catalyst is placed inside the first catalyst portion, the second catalyst portion, and the third catalyst portion; platinum loads of the pure platinum catalysts inside the first catalyst portion, the second catalyst portion, and the third catalyst portion decrease progressively; and average particle sizes of pure platinum catalyst particles inside the first catalyst portion, the second catalyst portion, and the third catalyst portion increase progressively. The pure platinum catalyst with a large or small particle size is more resistant to corrosion, and improves the initial performance of fuel cell.

Abstract: A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

Abstract: A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.

Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.