Patents by Inventor Guofeng Zhang

Guofeng Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7817151
    Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 19, 2010
    Assignee: VIA Technologies, Inc.
    Inventor: Guofeng Zhang
  • Patent number: 7812849
    Abstract: A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 12, 2010
    Assignee: VIA Technologies, Inc.
    Inventors: Guofeng Zhang, Xuan Zhao
  • Patent number: 7536348
    Abstract: A predictive model, for example, a neural network, evaluates individual debt holder accounts and predicts the amount that will be collected on each account based on learned relationships among known variables. The predictive model is generated using historical data of delinquent debt accounts, the collection methods used to collect the debts in the accounts, and the success of the collection methods. In one embodiment, the predictive model is generated using profiles of delinquent debt accounts summarizing patterns of events in the accounts, and the success of the collection effort in each account. In another embodiment, the predictive model includes a mathematical representation of the collector's notes created during the collection period for each account.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: May 19, 2009
    Assignee: Fair Isaac Corporation
    Inventors: Min Shao, Scott Zoldi, Gordon Cameron, Ron Martin, Radu Drossu, Jenny (Guofeng) Zhang, Daniel Shoham
  • Publication number: 20070156557
    Abstract: A predictive model, for example, a neural network, evaluates individual debt holder accounts and predicts the amount that will be collected on each account based on learned relationships among known variables. The predictive model is generated using historical data of delinquent debt accounts, the collection methods used to collect the debts in the accounts, and the success of the collection methods. In one embodiment, the predictive model is generated using profiles of delinquent debt accounts summarizing patterns of events in the accounts, and the success of the collection effort in each account. In another embodiment, the predictive model includes a mathematical representation of the collector's notes created during the collection period for each account.
    Type: Application
    Filed: March 8, 2007
    Publication date: July 5, 2007
    Inventors: Min Shao, Scott Zoldi, Gordon Cameron, Ron Martin, Radu Drossu, Jenny (Guofeng) Zhang, Daniel Shoham
  • Publication number: 20070106999
    Abstract: This invention discloses a method for assisting multi-threaded command execution by a driver in a multi-core, computer system, the method comprising distinguishing asynchronous commands from synchronous commands, buffering the asynchronous commands in a buffer, processing the synchronous commands directly in a CPU driver thread, processing the asynchronous commands from the buffer by one or more CPU work threads, wherein multiple threads of the multi-core computer system can be utilized at the same time; and managing the buffer after the buffer is processed by the CPU work thread, wherein the command executions appear to be just like single-threaded to application software.
    Type: Application
    Filed: October 17, 2006
    Publication date: May 10, 2007
    Inventor: Guofeng Zhang
  • Publication number: 20070091099
    Abstract: A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Inventors: Guofeng Zhang, Xuan Zhao
  • Publication number: 20070091090
    Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Inventor: Guofeng Zhang
  • Publication number: 20070091097
    Abstract: A method and system are disclosed for synchronizing two or more engines in a graphics processing unit (GPU). When issuing a command to an engine, a central processing unit (CPU) writes an event value representing the command into an element of an event memory associated with the engine. After executing the command, the engine modifies the content of the event memory in order to recognize the completion of the command execution. The CPU acquires the command execution status by reading the modified content of the event memory. With precise knowledge of the command execution status, the CPU can issue commands to various engines independently, hence the engines can run parallel.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Inventor: Guofeng Zhang
  • Publication number: 20070091098
    Abstract: This invention discloses a method and system for implementing transparent multi-buffering in multi-GPU graphics subsystems. The purpose of multi-buffering is to reduce GPU idle time. In one example, after rendering a first image by a first GPU in a back buffer, the first image is displayed by flipping to the back buffer. After that, the front buffer and back buffer are exchanged, and then shifting the back buffer and internal buffers in a predetermined sequence. A second image is rendered to current back buffer by a second GPU. The second image is displayed by flipping to a current back buffer. After that, the front buffer and back buffer are exchanged again, and shifting the back buffer and internal buffers again.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Inventors: Guofeng Zhang, Xuan Zhao
  • Publication number: 20070088856
    Abstract: A method and system are disclosed for employing deferred command issuing in a computer system with multiple peripheral processors operating with a peripheral device driver embedded in a multi-threaded central processor. After issuing a first command with a first event tag by the peripheral device driver, a second command is generated for a first peripheral processor by the peripheral device driver following the issuing of the first command. The second command is stored awaiting for the first event tag being returned, and the second command is issued when the first event tag is returned if the first and second commands need to be synchronized.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 19, 2007
    Inventor: Guofeng Zhang
  • Publication number: 20070085903
    Abstract: This invention discloses a system and method for displaying 3-D stereoscopic images, in which stereoscopic image data are processed separately by two graphic processing channels. The operation of the two channels is synchronized, so that the processed stereoscopic images are outputted simultaneously to be displayed either by a polarization system or a head-mounted LCD system. Such a display system allows a viewer's left eye to see only a left image and the right eye to see only the right image, yet seeing the same pair of stereoscopic images at the same time, to create a natural 3-D image illusion.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 19, 2007
    Inventor: Guofeng Zhang
  • Patent number: 7191150
    Abstract: A predictive model, for example, a neural network, evaluates individual debt holder accounts and predicts the amount that will be collected on each account based on learned relationships among known variables. The predictive model is generated using historical data of delinquent debt accounts, the collection methods used to collect the debts in the accounts, and the success of the collection methods. In one embodiment, the predictive model is generated using profiles of delinquent debt accounts summarizing patterns of events in the accounts, and the success of the collection effort in each account. In another embodiment, the predictive model includes a mathematical representation of the collector's notes created during the collection period for each account.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: March 13, 2007
    Assignee: Fair Isaac Corporation
    Inventors: Min Shao, Scott Zoldi, Gordon Cameron, Ron Martin, Radu Drossu, Jenny (Guofeng) Zhang, Daniel Shoham