Patents by Inventor Guofu Peng

Guofu Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling
    Patent number: 9479190
    Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 25, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kexin Luo, Xiaozhi Lin, Guofu Peng, Yu Shen, Gijung Ahn
  • Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling
    Publication number: 20160254821
    Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.
    Type: Application
    Filed: October 23, 2014
    Publication date: September 1, 2016
    Applicant: Lattice Semiconductor Corporation
    Inventors: Kexin Luo, Xiaozhi Lin, Guofu Peng, Yu Shen, Gijung Ahn