Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof includes a source structure, a drain structure, a gate structure, a bottom dielectric layer, a gate dielectric layer, a channel structure, and a metal nitride layer. The source structure and the drain structure are stacked in a vertical direction, and the gate structure is between the drain structure and the source structure. The bottom dielectric layer is disposed between the drain structure and the source structure. The channel structure is disposed between the drain structure and the source structure and is electrically connected the drain structure and the source structure, and the channel structure is partially disposed in the gate structure. The gate dielectric layer is disposed between the channel structure and the gate structure. The metal nitride layer is disposed between the gate dielectric layer and the gate structure.

Abstract: A three-dimensional memory device includes a substrate and a stack structure including alternating conductive layers and dielectric layers disposed on the substrate, and a memory string structure extending vertically through the stack structure. The memory string structure includes a conductive pillar and a storage layer disposed between the conductive pillar and the stack structure and surrounding the conductive pillar. The storage layer includes a plurality of first protruding portions at interfaces between the conductive layers and the dielectric layers.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed in the present invention. The semiconductor device includes a source structure; a gate structure disposed above the source structure; a first opening penetrates through the gate structure in a vertical direction; a semiconductor structure; a gate dielectric layer; an insulation structure; and a void. The semiconductor structure is partially disposed in the first opening, and at least a portion of the gate structure is located at two opposite sides of the semiconductor structure in a horizontal direction. The gate dielectric layer is disposed in the first opening and located between the semiconductor structure and the gate structure. At least a portion of the insulation structure is disposed in the first opening, at least a portion of the semiconductor structure is located between the insulation structure and the gate dielectric layer, and the void is located in the insulation structure.

Abstract: The present disclosure provides a three-dimensional memory device and a method of fabricating the same, which includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangements, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.

Abstract: A three-dimensional memory device includes a staircase structure comprising steps respectively comprising a conductive layers and a dielectric layer. A sidewall of the conductive layer is recessed from a sidewall of the dielectric layer to form a recess that exposes a portion of a bottom surface of the dielectric layer.