Abstract: A method and apparatus provides for compiling a plurality of shaders, each shader having a plurality of computer-readable statements, into a plurality of computer-executable instructions. In one example, the method and apparatus, using a computing device, receives the plurality of shaders used in a process pipeline for performing at least one shading function, determines a shader type of each of the plurality of shaders based on the at least one shading function, and compiles the plurality of shaders by generating the computer-executable instructions using data including a shader descriptor for each of the plurality of shaders, resulting in the shading functions of the plurality of shaders combined together.

Abstract: The present disclosure relates to the field of air rifles, and particularly to a gear-type air rifle gear cock structure, including a air cylinder, a gear cock controller, a rack, and a rack reset spring, the gear cock controller is fixedly connected with the air cylinder, and the rack is arranged between the air cylinder and the gear cock controller; the air cylinder includes a air cylinder body, a piston, and a magazine, the air cylinder body has a hollow structure with an air chamber inside, the piston is arranged in the air chamber inside the air cylinder body, the magazine communicates with the air chamber through an outlet pipe; two ends of the rack are a piston fixing end and a spring fixing end respectively, the piston fixing end is connected with the piston through a lug arranged at the piston fixing end, the spring fixing end is connected with the rack reset spring, two ends of the rack reset spring are respectively fixed on the rack and the air cylinder.

Abstract: The present disclosure relates to the field of air rifles, and particularly to a gear-type air rifle gear cock structure, including a air cylinder, a gear cock controller, a rack, and a rack reset spring, the gear cock controller is fixedly connected with the air cylinder, and the rack is arranged between the air cylinder and the gear cock controller; the air cylinder includes a air cylinder body, a piston, and a magazine, the air cylinder body has a hollow structure with an air chamber inside, the piston is arranged in the air chamber inside the air cylinder body, the magazine communicates with the air chamber through an outlet pipe; two ends of the rack are a piston fixing end and a spring fixing end respectively, the piston fixing end is connected with the piston through a lug arranged at the piston fixing end, the spring fixing end is connected with the rack reset spring, two ends of the rack reset spring are respectively fixed on the rack and the air cylinder.

Abstract: Techniques for improving memory utilization for communication between stages of a graphics processing pipeline are disclosed. The techniques include analyzing output instructions of a first shader program to determine whether any such output instructions output some data that is not used by a second shader program. The compiler performs data packing if gaps exist between used output data to reduce memory footprint. The compiler generates optimized output instructions in the first shader program and optimized input instructions in the second shader program to output the used data from the first shader program and input that data in the second shader program in a packed format based on information about usage of output data and data packing. If needed, the compiler inserts instructions to perform runtime checking to identify unused output data of the first shader program based on information not known at compile-time.

Abstract: Techniques for improving memory utilization for communication between stages of a graphics processing pipeline are disclosed. The techniques include analyzing output instructions of a first shader program to determine whether any such output instructions output some data that is not used by a second shader program. The compiler performs data packing if gaps exist between used output data to reduce memory footprint. The compiler generates optimized output instructions in the first shader program and optimized input instructions in the second shader program to output the used data from the first shader program and input that data in the second shader program in a packed format based on information about usage of output data and data packing. If needed, the compiler inserts instructions to perform runtime checking to identify unused output data of the first shader program based on information not known at compile-time.

Abstract: A method and apparatus of copying data from a first memory location to a second memory location includes performing a copy operation selected out of one or more copy operations. The copy operations include performing interleaved data copying, performing a full wavefront copy operation, copying all data to a local data store (LDS) prior to copying to the second memory location, or pipelining the data for copying. The copy operation is applied to copy the data from the first location to the second memory location.

Abstract: A power distribution priority controller and a controlling method of a photovoltaic power generation system. The controller includes a calculating unit configured to calculate an electric device priority list according to running state information of electric devices and photovoltaic power generation data and to determine a preferred power distribution schemes; a controlling unit configured to acquire in real time the running state information of all electric devices, and control the electric devices according to the preferred power distribution schemes determined by the calculating unit; a communicating unit configured to transmit the photovoltaic power generation data, the running state information of electric devices, and control command information; a storage unit configured to store, in time units, the photovoltaic power generation data, the running state information of electric devices, and the preferred power distribution schemes.

Abstract: Systems, apparatuses, and methods for performing run-time checking of access uniformity of vector memory access instructions are disclosed. A system includes a vector unit, a scalar unit, and a memory. The system performs a run-time check to determine if two or more threads of a wave have access uniformity to the memory prior to executing a vector memory access instruction for the wave on the vector unit. The system replaces the vector memory access instruction with a group of instructions responsive to determining that two or more threads of the wave have access uniformity to the memory. The group of instructions includes a scalar access instruction to memory followed by a cross-thread data sharing instruction. The scalar access instruction is executed on the scalar unit. Alternatively, the group of instructions can include a vector memory access instruction by only a single thread in each group having access uniformity.

Abstract: A method and apparatus provides for compiling a plurality of shaders, each shader having a plurality of computer-readable statements, into a plurality of computer-executable instructions. In one example, the method and apparatus, using a computing device, receives the plurality of shaders used in a process pipeline for performing at least one shading function, determines a shader type of each of the plurality of shaders based on the at least one shading function, and compiles the plurality of shaders by generating the computer-executable instructions using data including a shader descriptor for each of the plurality of shaders, resulting in the shading functions of the plurality of shaders combined together.

Abstract: Systems, apparatuses, and methods for performing run-time checking of access uniformity of vector memory access instructions are disclosed. A system includes a vector unit, a scalar unit, and a memory. The system performs a run-time check to determine if two or more threads of a wave have access uniformity to the memory prior to executing a vector memory access instruction for the wave on the vector unit. The system replaces the vector memory access instruction with a group of instructions responsive to determining that two or more threads of the wave have access uniformity to the memory. The group of instructions includes a scalar access instruction to memory followed by a cross-thread data sharing instruction. The scalar access instruction is executed on the scalar unit. Alternatively, the group of instructions can include a vector memory access instruction by only a single thread in each group having access uniformity.

Abstract: Techniques for culling primitives are provided herein. The techniques involve automatic generation of shader programs to be executed by an accelerated processing device. A just-in-time compiler automatically generates the shader programs based on a vertex shader program that is provided for use in the vertex shader stage of the graphics processing pipeline. The automatically generated shader programs include instructions from the vertex shader program that transform the positions of vertices provided as input to the graphics processing pipeline to generate transformed input vertices. The shader programs also include instructions to cull primitives based on the transformed input vertices. After generating the automatically generated shader programs, the software module transmits the automatically generated shader programs to the graphics processing pipeline for execution.

Abstract: A method and apparatus of copying data from a first memory location to a second memory location includes performing a copy operation selected out of one or more copy operations. The copy operations include performing interleaved data copying, performing a full wavefront copy operation, copying all data to a local data store (LDS) prior to copying to the second memory location, or pipelining the data for copying. The copy operation is applied to copy the data from the first location to the second memory location.

Abstract: Techniques for culling primitives are provided herein. The techniques involve automatic generation of shader programs to be executed by an accelerated processing device. A just-in-time compiler automatically generates the shader programs based on a vertex shader program that is provided for use in the vertex shader stage of the graphics processing pipeline. The automatically generated shader programs include instructions from the vertex shader program that transform the positions of vertices provided as input to the graphics processing pipeline to generate transformed input vertices. The shader programs also include instructions to cull primitives based on the transformed input vertices. After generating the automatically generated shader programs, the software module transmits the automatically generated shader programs to the graphics processing pipeline for execution.

Abstract: A power distribution priority controller and a controlling method of a photovoltaic power generation system. The controller includes a calculating unit configured to calculate an electric device priority list according to running state information of electric devices and photovoltaic power generation data and to determine a preferred power distribution schemes; a controlling unit configured to acquire in real time the running state information of all electric devices, and control the electric devices according to the preferred power distribution schemes determined by the calculating unit; a communicating unit configured to transmit the photovoltaic power generation data, the running state information of electric devices, and control command information; a storage unit configured to store, in time units, the photovoltaic power generation data, the running state information of electric devices, and the preferred power distribution schemes.