Abstract: An array substrate of a display device includes a pixel electrode layer on a substrate, which includes active pixel electrodes in an active display region; outermost active pixel electrodes include a first active pixel electrode including a first pixel electrode edge and a second pixel electrode edge; in a first direction, the first pixel electrode edge is between the second pixel electrode edge and a frame region. One of the array substrate and an opposite substrate of the display device includes a common electrode layer including a first extended common electrode which includes a first extended portion extending beyond the first active pixel electrode; a first extended portion edge of the first extended portion and a first substrate edge of the substrate respectively extend in a second direction; in the first direction, the first extended portion edge is located between the first substrate edge and the first pixel electrode edge.

Abstract: A DC/DC converter includes a soft start overshoot prevention mechanism. The DC/DC converter includes a DC/DC conversion circuit, an overshoot detection apparatus, a pulse width modulation generator, an error amplifier, and an integration circuit connected to an output port of the error amplifier. The integration circuit is configured to perform integration processing on a difference between a reference voltage and an output voltage of the DC/DC conversion circuit, and control an amplitude of an amplified voltage that is input by the error amplifier to the pulse width modulation generator. The overshoot detection apparatus obtains an operating status parameter of the DC/DC converter, and controls, when the operating status parameter of the DC/DC converter meets an operating status parameter requirement, the integration circuit to discharge.

Abstract: An apparatus is disclosed for adaptive switch driving. In an example aspect, the apparatus includes a switching circuit configured to selectively be in a first state that provides an input voltage as an output voltage, be in a second state that provides a ground voltage as the output voltage, or be in a third state that causes the output voltage to change from the input voltage to the ground voltage according to a slew rate. The third state enables the switching circuit to transition from the first state to the second state. The switching circuit is also configured to adjust the slew rate of the output voltage for the third state responsive to at least one of the following: a change in a magnitude of a direct-current supply voltage or a change in a magnitude of an input current.

Abstract: An apparatus is disclosed for adaptive switch driving. In an example aspect, the apparatus includes a switching circuit configured to selectively be in a first state that provides an input voltage as an output voltage, be in a second state that provides a ground voltage as the output voltage, or be in a third state that causes the output voltage to change from the input voltage to the ground voltage according to a slew rate. The third state enables the switching circuit to transition from the first state to the second state. The switching circuit is also configured to adjust the slew rate of the output voltage for the third state responsive to at least one of the following: a change in a magnitude of a direct-current supply voltage or a change in a magnitude of an input current.

Abstract: A multi-level direct current converter includes a direct current conversion unit, a switching unit, a voltage management unit, and a controller. The direct current conversion unit includes a flying capacitor, a first power transistor, and a second power transistor. A first end of the first power transistor is connected to a voltage input end of the multi-level direct current converter, a second end of the first power transistor is connected to a first end of the second power transistor by using the flying capacitor, and a second end of the second power transistor is connected to a reference ground.

Abstract: The three-level direct current converter includes: a flying capacitor, a plurality of switch groups, a drive circuit, and a control circuit. The control circuit includes at least an on-time generator. When a voltage on the flying capacitor deviates from a half of a power supply voltage, the on-time generator changes a charging current of a capacitor of the on-time generator to adjust an output on-time signal, and outputs the on-time signal to the drive circuit. The drive circuit generates a drive pulse signal based on the on-time signal to drive switch statuses of the plurality of switch groups, to adjust charging time and discharging time of the flying capacitor, where an absolute value of a difference between the voltage on the flying capacitor and the half of the power supply voltage is less than or equal to a preset threshold.

Abstract: A DC/DC converter includes a soft start overshoot prevention mechanism. The DC/DC converter includes a DC/DC conversion circuit, an overshoot detection apparatus, a pulse width modulation generator, an error amplifier, and an integration circuit connected to an output port of the error amplifier. The integration circuit is configured to perform integration processing on a difference between a reference voltage and an output voltage of the DC/DC conversion circuit, and control an amplitude of an amplified voltage that is input by the error amplifier to the pulse width modulation generator. The overshoot detection apparatus obtains an operating status parameter of the DC/DC converter, and controls, when the operating status parameter of the DC/DC converter meets an operating status parameter requirement, the integration circuit to discharge.

Abstract: An apparatus is disclosed for adaptive switch driving. In an example aspect, the apparatus includes a switching circuit configured to selectively be in a first state that provides an input voltage as an output voltage, be in a second state that provides a ground voltage as the output voltage, or be in a third state that causes the output voltage to change from the input voltage to the ground voltage according to a slew rate. The third state enables the switching circuit to transition from the first state to the second state. The switching circuit is also configured to adjust the slew rate of the output voltage for the third state responsive to at least one of the following: a change in a magnitude of a direct-current supply voltage or a change in a magnitude of an input current.

Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.

Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.

Abstract: A duty cycle estimation circuit includes a latch circuit that receives a clock signal for a voltage regulator. The latch circuit outputs a duty cycle estimate. The duty cycle estimation circuit also includes a low pass filter coupled to an output of the latch circuit to receive the duty cycle estimate. The duty cycle estimation circuit further includes a comparator that receives, as input, an output of the low pass filter and a voltage regulator output. The comparator feeds back a feedback signal to the latch circuit.

Abstract: Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Abstract: A duty cycle estimation circuit includes a latch circuit that receives a clock signal for a voltage regulator. The latch circuit outputs a duty cycle estimate. The duty cycle estimation circuit also includes a low pass filter coupled to an output of the latch circuit to receive the duty cycle estimate. The duty cycle estimation circuit further includes a comparator that receives, as input, an output of the low pass filter and a voltage regulator output. The comparator feeds back a feedback signal to the latch circuit.

Abstract: Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Abstract: The disclosed systems and methods for current management can be used with system-on-a-chip (SoC) integrated circuits in, for example, battery-powered portable devices. The current management provides detection of supply current levels from a power management integrated circuit (PMIC) to an SoC. The PMIC signals, for example, using interrupts, the SoC when the supply current levels exceed thresholds. The SoC can then alter its operations to avoid exceeding the current capability of the PMIC. The current management can avoid the SoC experiencing a functional failure due to loss of power during high current conditions. Additionally, development methods can be used to optimize a system for various conditions besides the traditional worst-case design commonly used.

Abstract: A method of controlling the charge of the bootstrap capacitor during light load or no load conditions for a non-synchronous type of DC-DC converter consists of bootstrap capacitor voltage detector, light load detector and secondary switch controller. By turning on the secondary switch during the off-time of the power transistor when the bootstrap voltage is lower than the required value under light load condition, the bootstrap capacitor voltage will be able to charge back to the required value, yet minimizing the minimum current requirement for the DC-DC converter.

Abstract: A method of controlling the charge of the bootstrap capacitor during light load or no load conditions for a non-synchronous type of DC-DC converter consists of bootstrap capacitor voltage detector, light load detector and secondary switch controller. By turning on the secondary switch during the off-time of the power transistor when the bootstrap voltage is lower than the required value under light load condition, the bootstrap capacitor voltage will be able to charge back to the required value, yet minimizing the minimum current requirement for the DC-DC converter.