Patents by Inventor Guoliang GONG

Guoliang GONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616336
    Abstract: A class of erbium-doped silicate crystals have a general chemical formula of (ErxYbyCezA(1-x-y-z))3RM3Si2O14, in which the range of x is 0.002 to 0.02, y is 0.005 to 0.1, and z is 0 to 0.15; A is one, two or three elements selected from Ca, Sr, or Ba; R is one or two elements selected from Nb or Ta; M is one or two elements selected from Al or Ga. Using one of such crystals as a gain medium and a diode laser at 940 nm or 980 nm as a pumping source, a 1.5 ?m continuous-wave solid-state laser with high output power and high efficiency, as well as a pulse solid-state laser with high energy and narrow width can be obtained.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 28, 2023
    Assignee: FUJIAN INSTITUTE OF RESEARCH ON THE STRUCTURE OF MATTER, CHINESE ACADEMY OF SCIENCES
    Inventors: Yidong Huang, Yujin Chen, Guoliang Gong, Jianhua Huang, Yanfu Lin, Xinghong Gong, Zundu Luo
  • Publication number: 20200280163
    Abstract: A class of erbium-doped silicate crystals have a general chemical formula of (ErxYbyCezA(1-x-y-z))3RM3Si2O14, in which the range of x is 0.002 to 0.02, y is 0.005 to 0.1, and z is 0 to 0.15; A is one, two or three elements selected from Ca, Sr, or Ba; R is one or two elements selected from Nb or Ta; M is one or two elements selected from Al or Ga. Using one of such crystals as a gain medium and a diode laser at 940 nm or 980 nm as a pumping source, a 1.5 ?m continuous-wave solid-state laser with high output power and high efficiency, as well as a pulse solid-state laser with high energy and narrow width can be obtained.
    Type: Application
    Filed: August 21, 2018
    Publication date: September 3, 2020
    Inventors: Yidong HUANG, Yujin CHEN, Guoliang GONG, Jianhua HUANG, Yanfu LIN, Xinghong GONG, Zundu LUO
  • Patent number: 8692387
    Abstract: A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shunan Qiu, Guoliang Gong, Xuesong Xu, Xingshou Pang, Beiyue Yan, Yinghui Li
  • Publication number: 20140024199
    Abstract: A method of producing semiconductor dies includes providing a semiconductor wafer having front and back faces and an array of integrated circuits fabricated on it. The integrated circuits having active faces at the front face of the wafer. Grooves are cut mechanically from the back face partially through the wafer along saw streets between the integrated circuits. The integrated circuits are then singulated by scanning a laser beam on the front face within and along the saw streets, which scribes the wafer from the front face, and then singulating the integrated circuits by mechanically cleaving the wafer along the saw streets.
    Type: Application
    Filed: November 19, 2012
    Publication date: January 23, 2014
    Inventors: Shunan QIU, Guoliang GONG, Jun LI, Haiyan LIU
  • Patent number: 8496158
    Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: July 30, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fei Zong, Guoliang Gong, Meiquan Huang, Hejin Liu
  • Publication number: 20130119114
    Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.
    Type: Application
    Filed: September 6, 2012
    Publication date: May 16, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Fei ZONG, Guoliang GONG, Meiquan HUANG, Hejin LIU
  • Publication number: 20130037966
    Abstract: A semiconductor device includes a semiconductor die having first and second opposing faces and an edge surface. The edge surface has an undercut under the first face. The second face of the semiconductor die is bonded to a bonding surface of a die support member, such as a thermally conductive flag of a lead frame, with a die attach material. A fillet of the bonding material is formed within the undercut.
    Type: Application
    Filed: June 13, 2012
    Publication date: February 14, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Shunan QIU, Guoliang Gong, Junhua Luo, Xuesong Xu
  • Publication number: 20130020690
    Abstract: A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
    Type: Application
    Filed: June 6, 2012
    Publication date: January 24, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Shunan QIU, Guoliang GONG, Xuesong XU, Xingshou PANG, Beiyue YAN, Yinghui LI