Patents by Inventor Guoliang Xie
Guoliang Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10994005Abstract: A novel K (capsular antigen) serotype of Vibrio parahaemolyticus and an application thereof are provided. A novel K (capsular antigen) serotype of Vibrio parahaemolyticus, which was deposited at the China General Microbiological Culture Collection Center (Institute of Microbiology, Chinese Academy of Sciences, No. 3, Yard 1, Beichen West Road, Chaoyang District, Beijing) on Feb. 20, 2019, with a deposit number of CGMCC No. 17249, wherein the K epitope of the Vibrio parahaemolyticus has a sequence set forth in Sequence No. 1. The novel K serum is highly specific, and can be used to conveniently and quickly detect a novel K serotype of Vibrio parahaemolyticus (O4:KUT-recAin) which has a rising infection rate in recent years. It provides important detection techniques for the pathogen diagnosis, monitoring and prevention of infectious diarrhea.Type: GrantFiled: July 30, 2019Date of Patent: May 4, 2021Assignee: ZHEJIANG UNIVERSITYInventors: Yu Chen, Xiao Chen, Qiaoyun Zhu, Guoliang Xie, Ruonan Wang
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Publication number: 20210052716Abstract: A novel K (capsular antigen) serotype of Vibrio parahaemolyticus and an application thereof are provided. A novel K (capsular antigen) serotype of Vibrio parahaemolyticus, which was deposited at the China General Microbiological Culture Collection Center (Institute of Microbiology, Chinese Academy of Sciences, No. 3, Yard 1, Beichen West Road, Chaoyang District, Beijing) on Feb. 20, 2019, with a deposit number of CGMCC No. 17249, wherein the K epitope of the Vibrio parahaemolyticus has a sequence set forth in Sequence No. 1. The novel K serum is highly specific, and can be used to conveniently and quickly detect a novel K serotype of Vibrio parahaemolyticus (O4:KUT-recAin) which has a rising infection rate in recent years. It provides important detection techniques for the pathogen diagnosis, monitoring and prevention of infectious diarrhea.Type: ApplicationFiled: July 30, 2019Publication date: February 25, 2021Applicant: Zhejiang UniversityInventors: Yu Chen, Xiao Chen, Qiaoyun Zhu, Guoliang Xie, Ruonan Wang
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Publication number: 20200395399Abstract: A packaging method and a packaging structure for a semiconductor chip. The packaging method comprises: providing a wafer, the water being provided with a functional area and solder pads arranged on a first surface; forming vias on a second surface of the wafer, the bottom of the vias exposing the solder pads; forming metal wiring layers at the bottom and on the sidewalls of the vias, the metal wiring layers extending to the second surface of the wafer, the metal wiring layers being electrically connected to the corresponding solder pads; forming a solder mask layer on the second surface of the wafer and in the vias; forming grooves on the solder mask layer at positions corresponding to the vias, the difference between the depth of the grooves and the depth of the vias being 0-20 micrometers.Type: ApplicationFiled: May 23, 2017Publication date: December 17, 2020Applicant: China Water Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu, Wenbin Wang
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Patent number: 10817700Abstract: An optical fingerprint recognition chip package and a packaging method are provided. In the optical fingerprint recognition chip package, a cover plate is arranged on a front surface of an optical fingerprint recognition chip, the cover plate includes a substrate and a light shielding layer. The light shielding layer is arranged on a surface of the substrate facing away from the optical fingerprint recognition chip. The substrate is provided with multiple first through holes for exposing photosensitive pixels of the optical fingerprint recognition chip. The light shielding layer is provided with multiple second through holes in one-to-one correspondence with the first through holes. During fingerprint recognition, light reflected by a finger is split through the first through holes and the second through holes, such that crosstalk among different photosensitive pixels is reduced, and the accuracy of fingerprint recognition is improved.Type: GrantFiled: December 5, 2018Date of Patent: October 27, 2020Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Publication number: 20200234028Abstract: An optical fingerprint recognition chip package and a packaging method are provided. In the optical fingerprint recognition chip package, a cover plate is arranged on a front surface of an optical fingerprint recognition chip, the cover plate includes a substrate and a light shielding layer. The light shielding layer is arranged on a surface of the substrate facing away from the optical fingerprint recognition chip. The substrate is provided with multiple first through holes for exposing photosensitive pixels of the optical fingerprint recognition chip. The light shielding layer is provided with multiple second through holes in one-to-one correspondence with the first through holes. During fingerprint recognition, light reflected by a finger is split through the first through holes and the second through holes, such that crosstalk among different photosensitive pixels is reduced, and the accuracy of fingerprint recognition is improved.Type: ApplicationFiled: December 5, 2018Publication date: July 23, 2020Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Patent number: 10541186Abstract: A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.Type: GrantFiled: April 11, 2018Date of Patent: January 21, 2020Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Patent number: 10541262Abstract: A package for an image sensing chip is provided, which includes: an image sensing chip comprising a first surface and a second surface opposite to each other, where the first surface is provided with an image sensing region and a contact pad; a through hole extending from the second surface to the contact pad; an electrical connection layer provided along an inner wall of the through hole and extending onto the second surface; a solder mask filling the through hole and covering the electrical connection layer, wherein an opening is formed in the solder mask, and the electrical connection layer is exposed at a bottom of the opening; a guide contact pad covering an inner wall and the bottom of the opening and extending onto the solder mask; and a solder bump located on the guide contact pad.Type: GrantFiled: September 19, 2016Date of Patent: January 21, 2020Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
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Publication number: 20190296064Abstract: Provided are a packaging method and packaging structure for a semiconductor chip. The packaging method comprises: providing a wafer, the wafer being provided with multiple semiconductor chips, each semiconductor chip being provided with a functional area and solder pads arranged on a first surface; providing a protective substrate, multiple support units being provided on the protective substrate, openings being formed on the support units; aligning the solder pads to the openings and facing support units provided on the protective substrate to the first surface of the wafer, and pressing together the wafer and the protective substrate. The packaging method effectively prevents the support units from generating stress that acts on the solder pads in a subsequent reliability test, thus preventing cases of the solder pad being damaged or split into layers.Type: ApplicationFiled: May 18, 2017Publication date: September 26, 2019Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu, Wenbin Wang
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Publication number: 20190188447Abstract: An optical fingerprint recognition chip package and a packaging method are provided. In the optical fingerprint recognition chip package, a cover plate is arranged on a front surface of an optical fingerprint recognition chip, the cover plate includes a substrate and a light shielding layer. The light shielding layer is arranged on a surface of the substrate facing away from the optical fingerprint recognition chip. The substrate is provided with multiple first through holes for exposing photosensitive pixels of the optical fingerprint recognition chip. The light shielding layer is provided with multiple second through holes in one-to-one correspondence with the first through holes. During fingerprint recognition, light reflected by a finger is split through the first through holes and the second through holes, such that crosstalk among different photosensitive pixels is reduced, and the accuracy of fingerprint recognition is improved.Type: ApplicationFiled: December 5, 2018Publication date: June 20, 2019Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Patent number: 10325946Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.Type: GrantFiled: September 28, 2016Date of Patent: June 18, 2019Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
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Patent number: 10283483Abstract: A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each having an image sensing region and contact pads arranged on a side of the first surface of the wafer; forming openings extending towards the first surface on the second surface of the wafer, to expose the contact pads; forming V-shaped cutting trenches extending towards the first surface on the second surface of the wafer; and applying a photosensitive ink on the second surface of the wafer, to completely fill the V-shaped cutting trenches, cover the openings, and form a hollow cavity between each of the openings and the photosensitive ink.Type: GrantFiled: September 29, 2016Date of Patent: May 7, 2019Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
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Publication number: 20190074309Abstract: A package for an image sensing chip is provided, which includes: an image sensing chip comprising a first surface and a second surface opposite to each other, where the first surface is provided with an image sensing region and a contact pad; a through hole extending from the second surface to the contact pad; an electrical connection layer provided along an inner wall of the through hole and extending onto the second surface; a solder mask filling the through hole and covering the electrical connection layer, wherein an opening is formed in the solder mask, and the electrical connection layer is exposed at a bottom of the opening; a guide contact pad covering an inner wall and the bottom of the opening and extending onto the solder mask; and a solder bump located on the guide contact pad.Type: ApplicationFiled: September 19, 2016Publication date: March 7, 2019Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
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Publication number: 20190067352Abstract: An image sensor chip package and a packaging method thereof are provided. The image sensor chip package includes: an image sensor chip having a first surface and a second surface opposite to each other, a photosensitive region being arranged on the first surface; a protective cover plate having a third surface and a fourth surface opposite to each other, the third surface covering the first surface; and a light shielding layer arranged on the fourth surface of the protective cover plate, the light shielding layer having an opening, and the photosensitive region being exposed through the opening. The light shielding layer includes a light absorbing layer located on the fourth surface and a metal layer located on the light absorbing layer.Type: ApplicationFiled: October 28, 2016Publication date: February 28, 2019Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie
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Publication number: 20190013302Abstract: A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure.Type: ApplicationFiled: July 6, 2018Publication date: January 10, 2019Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Publication number: 20180366387Abstract: A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.Type: ApplicationFiled: April 11, 2018Publication date: December 20, 2018Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Hanqing Hu
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Publication number: 20180301434Abstract: A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each having an image sensing region and contact pads arranged on a side of the first surface of the wafer; forming openings extending towards the first surface on the second surface of the wafer, to expose the contact pads; forming V-shaped cutting trenches extending towards the first surface on the second surface of the wafer; and applying a photosensitive ink on the second surface of the wafer, to completely fill the V-shaped cutting trenches, cover the openings, and form a hollow cavity between each of the openings and the photosensitive ink.Type: ApplicationFiled: September 29, 2016Publication date: October 18, 2018Applicant: China Water Level CSP Co., Ltd.Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
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Publication number: 20180301488Abstract: A package and a packaging method for an image sensing chip are provided. The package includes: an image sensing chip having a first surface and a second surface opposite to each other, where the first surface is provided with an image sensing region and a contact pad around the image sensing region; a through hole extending from the second surface to the contact pad; a passivation layer provided on a side wall of the through hole and on the second surface; an electrical connection layer provided on a bottom of the through hole and on the passivation layer, where the electrical connection layer is electrically connected with the contact pad; and a solder bump electrically connected with the electrical connection layer.Type: ApplicationFiled: October 28, 2015Publication date: October 18, 2018Applicant: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Guoliang Xie, Zhixiong Jin, Junjie Li
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Publication number: 20180286903Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.Type: ApplicationFiled: September 28, 2016Publication date: October 4, 2018Applicant: China Wafer Level CSP Co., LtdInventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie