Abstract: The invention discloses a method of preparing a high chiral purity lactam intermediate D comprising a step of reducing a compound C to lactam intermediate D in a solvent by hydrogenation reduction using a heavy metal catalyst and a chiral inducer. Brivaracetam can be prepared in a single step using the lactam intermediate D. The synthesis route is short, reaction conditions are mild, post-treatment is simple, reaction yield is high, chiral selectivity is good, and production cost is low. The conversion rate of the compound C in the reaction is 81%, and the DE value of the compound D is more than 99.0%, which is suitable for industrial production.

Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.

Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.

Abstract: The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance between the connection lead and the solder pad. The present invention meets a tendency of increasing quantity per area of peripheral arrayed compatible pads and solder bumps on a semiconductor chip, and also saves more space for layout of leads on the chip bottom surface so as to avoid potential short circuit in between which happens in increasing probability with increasing quantity per area on the condition of the lead and the solder bump.