Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data to be stored on the non-volatile memory device; a first non-volatile memory block and a second non-volatile memory block, the first non-volatile memory block and the second non-volatile memory block being provided on a single die, wherein the first non-volatile memory block and second non-volatile memory block are of a different type such that the first non-volatile memory block and the second non-volatile memory block require incompatible external attack techniques in order to retrieve data there from; and—an encryption circuit for encrypting the external data forming encrypted data using unique data from at least the first non-volatile memory block as an encryption key, the encrypted data at least being stored into the second non-volatile memory block. The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.

Abstract: A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.

Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.

Abstract: A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.

Abstract: A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1?, D1?) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D) to be stored on the non-volatile memory device; a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from; and—an encryption circuit (50) for encrypting the external data (D) forming encrypted data (D?, D?) using unique data (K, K1, K2) from at least the first non-volatile memory block (100) as an encryption key, the encrypted data (D?, D?) at least being stored into the second non-volatile memory block (200).

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1?, D1?) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:—a group of said memory cells is connected in parallel,—the source terminals of the memory cells in the group are connected together and to a source line,—the drain terminals of the memory cells in the group are connected together and to a drain line,—the gate terminals of the memory cells in the group are connected together and to a gate line, and—said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.

Abstract: There is a test structure on a semiconductor substrate for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device. In an example embodiment, the test structure includes a first and a second triple well structure; the second triple well structure is adjacent to the first triple well-structure in a first direction. Each structure includes a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region, wherein a central base portion and a central n-well region portion are common to the first and the second structure, with the central base portion as a symmetry line with a width. Between the central base portion and the p-well region in the first triple well-structure a first overlay, and between the central base portion and the p-well region in the second triple well-structure a second overlay is provided.

Abstract: The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:—a group of said memory cells is connected in parallel,—the source terminals of the memory cells in the group are connected together and to a source line,—the drain terminals of the memory cells in the group are connected together and to a drain line,—the gate terminals of the memory cells in the group are connected together and to a gate line, and—said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.

Abstract: Test structure (1), on a semiconductor substrate, for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device, including a first (T1) and a second (T2) triple well-structure, the second triple well-structure (T2) adjacent to the first triple well-structure (T1) in a first direction (D1), each structure (T1; T2) including a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region,

Abstract: The invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element (1), formed on a semiconductor surface (2), for storing a data bit; the non-volatile memory element (1) including a fuse wire (3) and a heating wire (4); the fuse wire (3) being arranged as a planar line, and further being arranged as a memory element to be programmable by blowing the fuse wire (3) through joule heating induced by a current flow; the heating wire (4) being arranged as a heater spatially surrounding the fuse wire (3), and the heating wire (4) being arranged to generate additional heat by current flow induced joule heating and to provide said additional heat to the fuse wire (3) during programming of the fuse wire (3).

Abstract: A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR) a read transistor (TRE), a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi_p, Vsi_e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).

Abstract: The invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element (1), formed on a semiconductor surface (2), for storing a data bit; the non-volatile memory element (1) including a fuse wire (3) and a heating wire (4); the fuse wire (3) being arranged as a planar line, and further being arranged as a memory element to be programmable by blowing the fuse wire (3) through joule heating induced by a current flow; the heating wire (4) being arranged as a heater spatially surrounding the fuse wire (3), and the heating wire (4) being arranged to generate additional heat by current flow induced joule heating and to provide said additional heat to the fuse wire (3) during programming of the fuse wire (3).