Abstract: A high-temperature wide-bandgap power module and a preparation method thereof is provided in the present application. In the high-temperature wide-bandgap power module, SiC power chips are arranged in the cavity, and bonding wires are used to establish electrical connections. An ultrathin composite conformal coating consists of inorganic film and Parylene-HT film is arranged on the surface of the circuit to provide long-term reliable insulation while only imposing minor thermo-mechanical stresses on bonding joint at high-temperatures, which prolongs the module's life time. In addition, the hermetic sealing adopted in the present application blocks the external water, oxygen and chemical pollution, thereby alleviating the thermal degradation of the conformal coating and safeguards the internal circuit. Overall, the hermetic sealing and conformal coating ensure the long-term 250 degrees high-temperature working capability of the wide-bandgap power module.

Abstract: The present disclosure relates to the technical field of heat dissipation for electronic devices, and discloses a manifold microchannel heat sink based on directional optimization of hotspot areas, including a power module, a heat dissipation substrate, a cold source device, and a diverter manifold; the heat dissipation substrate is arranged on the power module, a microchannel is provided on a side of the heat dissipation substrate away from the power module and on a back of a heat generating area of the power module for carrying the power module and dissipating heat from the power module. According to the manifold microchannel heat sink based on the directional optimization of hotspot areas, the local heat dissipation performance of the power module may be preliminarily changed by optimizing the microchannel on the heat dissipation substrate, which avoids poor heat dissipation temperature uniformity in a multi-heat source system.

Abstract: The present invention belongs to the technical field of simulation of power semiconductor modules, and discloses a multi-physics co-simulation method of a power semiconductor module. The multi-physics co-simulation method of the power semiconductor module comprises: adopting professional circuit simulation software PSpice supporting a spice model to be imported into a device, and by designing a specific collaborative analysis method and performing secondary development of a software data exchange interface, i.e. constructing a coupling interface of co-simulation, performing electricity-heat-force co-simulation of two types of software PSpice and COMSOL by adopting an indirect coupling manner. The simulation time is greatly shortened, and the simulation efficiency is improved.

Abstract: The present disclosure relates to the technical field of heat dissipation for electronic devices, and discloses a manifold microchannel heat sink based on directional optimization of hotspot areas, including a power module, a heat dissipation substrate, a cold source device, and a diverter manifold; the heat dissipation substrate is arranged on the power module, a microchannel is provided on a side of the heat dissipation substrate away from the power module and on a back of a heat generating area of the power module for carrying the power module and dissipating heat from the power module. According to the manifold microchannel heat sink based on the directional optimization of hotspot areas, the local heat dissipation performance of the power module may be preliminarily changed by optimizing the microchannel on the heat dissipation substrate, which avoids poor heat dissipation temperature uniformity in a multi-heat source system.

Abstract: The present disclosure belongs to the technical field of power electronic converters, and discloses a method and a system for predicting a junction temperature of a power semiconductor module in the full life cycle and a terminal. The method includes the steps: arranging an NTC thermistor network to monitor the temperature of each area inside the power module when the power module works; obtaining data for training the neural network by utilizing finite element simulation or experiments, and building a neural network model among the temperature of the NTC resistor network, a water flow rate, an aging factor and the junction temperature of the chip under working conditions. The present disclosure improves the junction temperature prediction accuracy of areas with relatively large errors comprehensively and realizes the high-precision junction temperature prediction under all working conditions.

Abstract: The present invention belongs to the technical field of gate driving circuits, and discloses a partially bootstrapped gate driving circuit for reducing switching loss and a control method thereof. The partially bootstrapped gate driving circuit for reducing the switching loss comprises a switching device, PWM, a power supply, signal isolation, non-isolated driving chips, a bootstrap structure, a driving resistor, Mon and Moff. The bootstrap structure is used in the present invention, which can realize voltage doubling output without increasing the power supply, overcomes limitation of parasitic resistance inside a large gate of a wide band gap device, and can significantly reduce the switching loss.

Abstract: The present invention belongs to the technical field of simulation of power semiconductor modules, and discloses a multi-physics co-simulation method of a power semiconductor module. The multi-physics co-simulation method of the power semiconductor module comprises: adopting professional circuit simulation software PSpice supporting a spice model to be imported into a device, and by designing a specific collaborative analysis method and performing secondary development of a software data exchange interface, i.e. constructing a coupling interface of co-simulation, performing electricity-heat-force co-simulation of two types of software PSpice and COMSOL by adopting an indirect coupling manner. The simulation time is greatly shortened, and the simulation efficiency is improved.

Abstract: Embodiments of the invention relate generally to graphene fibers and, more particularly, to graphene fibers comprising intercalated large-sized graphene oxide (LGGO)/graphene sheets and small-sized graphene oxide (SMGO)/graphene sheets having high thermal and electrical conductivities and high mechanical strength. In one embodiment, the invention provides a graphene fiber comprising: a plurality of intercalated graphene sheets including: a plurality of large-sized graphene sheets; and a plurality of small-sized graphene sheets, wherein at least one of the plurality of small-sized graphene sheets is disposed between at least two of the plurality of large-sized graphene sheets.

Abstract: Embodiments of the invention relate generally to graphene fibers and, more particularly, to graphene fibers comprising intercalated large-sized graphene oxide (LGGO)/graphene sheets and small-sized graphene oxide (SMGO)/graphene sheets having high thermal and electrical conductivities and high mechanical strength. In one embodiment, the invention provides a graphene fiber comprising: a plurality of intercalated graphene sheets including: a plurality of large-sized graphene sheets; and a plurality of small-sized graphene sheets, wherein at least one of the plurality of small-sized graphene sheets is disposed between at least two of the plurality of large-sized graphene sheets.