Patents by Inventor Guorjuh Thomas Hwang

Guorjuh Thomas Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits, integrated circuits, and methods for interleaved parity computation
    Patent number: 9166625
    Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Guorjuh Thomas Hwang, Chia Jen Chang
  • CIRCUITS, INTEGRATED CIRCUITS, AND METHODS FOR INTERLEAVED PARITY COMPUTATION
    Publication number: 20140331110
    Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Guorjuh Thomas Hwang, Chia Jen Chang
  • Circuits, integrated circuits, and methods for interleaved parity computation
    Patent number: 8806316
    Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Guorjuh Thomas Hwang, Chia Jen Chang
  • CIRCUITS, INTEGRATED CIRCUITS, AND METHODS FOR INTERLEAVED PARITY COMPUTATION
    Publication number: 20130179758
    Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Inventors: Guorjuh Thomas Hwang, Chia Jen Chang