Abstract: A printer includes a first power input, a second power input, a printing engine, and a controller. The first power input is configured to receive a first electric power from an external power supply. The second power input is configured to receive a second electric power from a secondary battery. The printing engine is configured to perform printing on a medium. The controller is configured to perform selectively executing one of a plurality of different modes. The plurality of different modes includes a first printing mode and a second printing mode. In the first printing mode, the controller controls the printing engine to perform printing using the first electric power without using the second electric power. In the second printing mode, the controller controls the printing engine to perform printing using both the first electric power and the second electric power.

Abstract: A shift register unit and a driving method thereof, a scan driving circuit, an array substrate and a display device. The shift register unit includes: an input circuit configured for setting the first node to a valid level in a case where the input terminal is at a valid level; a first reset control circuit configured for setting the second node to a valid level and setting the input terminal to an invalid level in a case where the reset terminal is at a valid level; an output circuit configured for setting the output terminal to a valid level by using a clock signal in a case where the first node is at the valid level; a reset circuit configured for setting the first node and the output terminal to an invalid level in a case where the second node is at a valid level.

Abstract: A shift register unit and a driving method thereof, a scan driving circuit, an array substrate and a display device. The shift register unit includes: an input circuit configured for setting the first node to a valid level in a case where the input terminal is at a valid level; a first reset control circuit configured for setting the second node to a valid level and setting the input terminal to an invalid level in a case where the reset terminal is at a valid level; an output circuit configured for setting the output terminal to a valid level by using a clock signal in a case where the first node is at the valid level; a reset circuit configured for setting the first node and the output terminal to an invalid level in a case where the second node is at a valid level.