Abstract: A VCSEL may include an n-type substrate layer and an n-type bottom mirror on a surface of the n-type substrate layer. The VCSEL may include an active region on the n-type bottom mirror and a p-type layer on the active region. The VCSEL may include an oxidation layer over the active region to provide optical and electrical confinement of the VCSEL. The VCSEL may include a tunnel junction over the p-type layer to reverse a carrier type of an n-type top mirror. Either the oxidation layer is on or in the p-type layer and the tunnel junction is on the oxidation layer, or the tunnel junction is on the p-type layer and the oxidation layer is on the tunnel junction. The VCSEL may include the n-type top mirror over the tunnel junction, a top contact layer over the n-type top mirror, and a top metal on the top contact layer.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) includes a substrate layer and epitaxial layers on the substrate layer. The epitaxial layers may include an active layer, a first mirror, a second mirror, and one or more oxidation layers. The active layer may be between the first mirror and the second mirror, and the one or more oxidation layers may be proximate to the active layer. The one or more oxidation layers may be configured to control beam divergence of a laser beam emitted by the VCSEL based on at least one of: a quantity of the one or more oxidation layers, a shape of the one or more oxidation layers, a thickness of the one or more oxidation layers, or a proximity of the one or more oxidation layers to the active layer.

Abstract: A wafer may comprise a substrate layer and a plurality of vertical cavity surface emitting lasers (VCSELs) formed on or within the substrate layer. A respective trench-to-trench distance associated with the plurality of VCSELs may vary across the wafer based on a predicted variation of an oxidation rate of an oxidation layer across the wafer.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) includes a substrate layer and epitaxial layers on the substrate layer. The epitaxial layers may include an active layer, a first mirror, a second mirror, and one or more oxidation layers. The active layer may be between the first mirror and the second mirror, and the one or more oxidation layers may be proximate to the active layer. The one or more oxidation layers may be configured to control beam divergence of a laser beam emitted by the VCSEL based on at least one of: a quantity of the one or more oxidation layers, a shape of the one or more oxidation layers, a thickness of the one or more oxidation layers, or a proximity of the one or more oxidation layers to the active layer.

Abstract: A semiconductor vertical resonant cavity light source includes an upper mirror and a lower mirror that define a vertical resonant cavity. A first active region is within the vertical resonant cavity for light generation between the upper mirror and lower mirror. The vertical resonant cavity includes an inner mode confinement region and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) is within the outer current blocking region of at least one of the upper mirror, lower mirror, and first active region. A conducting channel within the inner mode confinement region is framed by the DHCBR. The DHCBR forces current flow into the conducting channel during operation of the light source. A cavity length within the inner mode confinement region equals or exceeds the cavity length formed in the DHCBR.

Abstract: Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or coloring routing track(s). Some embodiments route the physical design with coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Multiple-patterning conflicts may be detected based on the coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Some embodiments route with search-and-repair strategy(ies) to improve or resolve conflict(s). Some embodiments color objects upon their creation, and the layout is thus multiple-patterning design rule clean as constructed.