Abstract: The present application discloses a thin film transistor, a preparation method thereof, an array substrate and a display panel. The thin film transistor provided in the present application includes an active layer, the active layer includes a plurality of sub-active layers, the plurality of sub-active layers are stacked along a first direction, each sub-active layer includes a crystalline oxide material, and atomic percentage of indium element in adjacent sub-active layers is different.

Abstract: The present disclosure provides a thin film transistor, a preparation method thereof, an array substrate, and a display panel. The thin film transistor includes a substrate, and an active layer and a first gate electrode located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, a mobility of the second film layer is lower than a mobility of the first film layer, and a roughness of the second film layer is less than a roughness of the first film layer.

Abstract: The present disclosure provides a thin film transistor and a manufacturing method therefor, an array substrate, and a display panel. The thin film transistor includes a substrate and an active layer and a first gate electrode both located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the second film layer has a lower mobility than the first film layer, and the second film layer has a larger density than the first film layer.

Abstract: Embodiments of the present application provide an array substrate and a preparation method therefor, and a display panel. The array substrate includes: a substrate; a first semiconductor layer located on one side of the substrate, the first semiconductor layer including a first active portion; a first insulating layer located on a side of the first semiconductor layer facing away from the substrate; a second semiconductor layer located on a side of the first insulating layer facing away from the first semiconductor layer, the second semiconductor layer including a second active portion; wherein a carrier mobility of one of the first active portion and the second active portion is greater than that of the other.

Abstract: The present application provides an array substrate, a preparation method for an array substrate, and a display panel. The array substrate includes a substrate, a first insulation layer, a planarization layer, a semiconductor layer, a source layer, and a drain layer. The first insulation layer is disposed on one side of the substrate, and the planarization layer, the semiconductor layer, the source layer, and the drain layer are each disposed on a side of the first insulation layer away from the substrate. The source layer is electrically connected to the drain layer via the semiconductor layer. The semiconductor layer includes a first semiconductor sublayer, the first semiconductor sublayer includes at least a crystalline semiconductor material, and at least part of the first semiconductor sublayer is stacked on a side of the planarization layer facing away from the substrate.

Abstract: Embodiments of the present disclosure disclose a thin-film transistor, a pixel circuit, a driving method for a pixel circuit, and a display panel. The thin-film transistor is applied to a pixel circuit, and the thin-film transistor includes a first gate and a second gate, the first gate and the second gate being located on two opposite sides of an active layer of the thin-film transistor, where the first gate is applied with a data voltage, and the second gate is configured to: use at least two different voltages within different preset grayscale intervals, and use the same voltage within the same preset grayscale interval.

Abstract: The present application provides a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. Two semiconductor layers having different carrier mobilities are provided, the semiconductor layer having a lower carrier mobility covers the semiconductor layer having a higher carrier mobility, and the semiconductor layer having a higher carrier mobility is located within the coverage area of a first electrode.

Abstract: A thin film transistor and a preparation method thereof, a display panel, and a display device. The thin film transistor includes an active structure and a gate that are stacked and insulated by an interlayer insulating layer, the active structure includes a source region, a drain region, and a channel region, the source region and the drain region are located on two sides of the channel region, and in a thickness direction of the interlayer insulating layer, a projection of the gate overlaps with a projection of the channel region; wherein the channel region includes a metal oxide material, a ratio of a number of indium atoms and a number of zinc atoms in the channel region is a, and a?4.

Abstract: The disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a display panel, and a display apparatus. The thin film transistor includes: an active layer provided on a substrate. The active layer includes a first semiconductor layer, a first barrier layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is located on a side, away from the substrate, of the second semiconductor layer, and a mobility rate of the first semiconductor layer is less than a mobility rate of the second semiconductor layer. A double channel is formed by providing the first barrier layer provided between the first semiconductor layer and the second semiconductor layer, so as to make a threshold voltage Vth positive and improve the mobility rate of the thin film transistor, so that a greater processing Margin may be accommodated, thereby ensuring stability of a device.

Abstract: A thin film transistor, a manufacturing method for the thin film transistor, and a display device are provided. The thin film transistor includes a substrate, and further includes an oxide semiconductor layer, a gate electrode, a gate insulation layer, a source electrode, and a drain electrode that are disposed on the substrate. The oxide semiconductor layer includes a channel portion, a first contact portion, and a second contact portion, where the source electrode is in contact with the first contact portion, and the drain electrode is in contact with the second contact portion. The channel portion at least partially protrudes in a direction away from the substrate, and the gate insulation layer and the gate electrode are successively stacked on the channel portion.

Abstract: An array substrate, a manufacturing method for the array substrate, and the display device are provided. The array substrate includes a substrate. The substrate includes at least one first region and at least one second region. A low temperature poly-silicon thin film transistor is disposed in the at least one first region, and an oxide thin film transistor is disposed in the at least one second region. The oxide-TFT includes an oxide semiconductor layer, a gate insulation layer, a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer includes a channel portion and contact portions connected to the channel portion. The channel portion, the gate insulation layer, and the gate electrode are sequentially stacked. The contact portions are respectively in contact with the source electrode and the drain electrode, and the channel portion at least partially protrudes in a direction away from the substrate.

Abstract: An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.

Abstract: An array substrate, a fabrication method thereof, and a display panel are provided. The array substrate comprises a substrate, and a plurality of thin-film-transistors, which includes an active layer formed on the substrate including a source region, a drain region, and a channel region located between the source region and the drain region, a source electrode metal contact layer, a drain electrode metal contact layer, a barrier layer formed on a side of the active layer facing away from the substrate, a source electrode formed on a side of the source electrode metal contact layer facing away from active layer, a drain electrode formed on a side of the drain electrode metal contact layer facing away from the active layer, and a gate electrode insulated from the barrier layer and formed on a side of the barrier layer facing away from the active layer.