Abstract: An inspection system and methods in which analog image data values (charges) captured by an image sensor are binned (combined) before or while being transmitted as output signals on the image sensor's output sensing nodes (floating diffusions), and in which an ADC is controlled to sequentially generate multiple corresponding digital image data values between each reset of the output sensing nodes. According to an output binning method, the image sensor is driven to sequentially transfer multiple charges onto the output sensing nodes between each reset, and the ADC is controlled to convert the incrementally increasing output signal after each charge is transferred onto the output sensing node. According to a multi-sampling method, multiple charges are vertically or horizontally binned (summed/combined) before being transferred onto the output sensing node, and the ADC samples each corresponding output signal multiple times. The output binning and multi-sampling methods may be combined.

Abstract: A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.

Abstract: An inspection system and methods in which analog image data values (charges) captured by an image sensor are binned (combined) before or while being transmitted as output signals on the image sensor's output sensing nodes (floating diffusions), and in which an ADC is controlled to sequentially generate multiple corresponding digital image data values between each reset of the output sensing nodes. According to an output binning method, the image sensor is driven to sequentially transfer multiple charges onto the output sensing nodes between each reset, and the ADC is controlled to convert the incrementally increasing output signal after each charge is transferred onto the output sensing node. According to a multi-sampling method, multiple charges are vertically or horizontally binned (summed/combined) before being transferred onto the output sensing node, and the ADC samples each corresponding output signal multiple times. The output binning and multi-sampling methods may be combined.

Abstract: A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.

Abstract: The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.

Abstract: A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.

Abstract: A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.

Abstract: A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.

Abstract: The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.

Abstract: A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.