Patents by Inventor Guoyuan LI

Guoyuan LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240165566
    Abstract: A polymer ultrafiltration membrane with a bicontinuous highly interconnected porous structure, a preparation method and applications thereof are provided. The ultrafiltration membrane has a bottom layer and a polymer layer. The polymer layer is divided into a sublayer and a surface layer. The surface layer is of a uniform small pore structure with a narrow pore size distribution. The sublayer is of a bicontinuous highly interconnected three-dimensional network porous structure. The bicontinuous highly interconnected porous structure of the bicontinuous highly interconnected porous ultrafiltration membrane is characterized as follows: in the thickness direction of the sublayer, the cross-sectional porosity on any XY cross-section perpendicular to the thickness direction is 40-90%, preferably 60-90%, and further preferably 70-90%; and the difference in the cross-sectional porosities between any two XY cross-sections does not exceed 10%, preferably not exceed 8%, and also preferably not exceed 5%.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 23, 2024
    Inventors: Yiqun LIU, Yu LI, Changjiang WU, Guoyuan PAN, Yang ZHANG, Hao YU, Muhua ZHAO
  • Publication number: 20220182021
    Abstract: The present disclosure discloses a thin film transistor (TFT)-based bootstrap structure amplifier, and a chip. The amplifier includes an input circuit, an output buffer, and several bootstrap structure units. The bootstrap structure units include a TFT and a capacitor. The drain and the gate of the TFT are both connected to the same voltage node. The source of the TFT is connected to one end of the capacitor. The other end of the capacitor is connected to an output signal node. The output buffer is formed by connecting the sources and drains of several TFTs in series. Two ends of the output buffer are respectively connected to an input voltage node and an output signal node. The source of the TFT in each bootstrap structure unit is connected to the gates of the TFTs in one output buffer. The input circuit includes an input signal node, the output signal node, and a grounding node. The present disclosure can increase circuit gain and have a simple structure and low fabrication cost.
    Type: Application
    Filed: December 31, 2019
    Publication date: June 9, 2022
    Inventors: Rongsheng CHEN, Houbo FAN, Guoyuan LI, Yuming XU, Yuning QIN, Zhaohui WU, Bin LI
  • Patent number: D1026183
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 7, 2024
    Inventors: Yaodong Li, Chenglong Zhou, Guoyuan Li, Yizhe Ren