Abstract: In some aspects, the present disclosure provides a method of allocating memory resources on a system-on-chip (SoC). The method includes receiving audio data from a first master, the first master being an audio subsystem. The method further includes receiving non-multimedia data from a second master, the second master being a non-multimedia subsystem. The method also includes communicating the audio data to a first partition of the memory management unit circuit, where the first partition is configured to be accessible by the first master and not the second master. The method further includes communicating the non-multimedia data to a second partition of the memory management unit circuit, where the second partition is configured to be accessible by the second master and not the first master, and where communication of the audio data is prioritized over communication of the non-multimedia data.

Abstract: A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.

Abstract: A system for reducing dynamic power consumption of a wakeup source includes a receiver interface coupled to the wakeup source. A data packet, received by the receiver interface, transmits the data packet to the wakeup source. The wakeup source processes the data packet to identify a predetermined code for initiating a wakeup sequence. The wakeup source is put into a deep sleep mode if it is idle for a predetermined time period.

Abstract: A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.

Abstract: A system for reducing dynamic power consumption of a wakeup source includes a receiver interface coupled to the wakeup source. A data packet, received by the receiver interface, transmits the data packet to the wakeup source. The wakeup source processes the data packet to identify a predetermined code for initiating a wakeup sequence. The wakeup source is put into a deep sleep mode if it is idle for a predetermined time period.