Patents by Inventor Gurgen Harutyunyan
Gurgen Harutyunyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096435Abstract: A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Grigor TSHAGHARYAN, Gurgen HARUTYUNYAN, Arun KUMAR, Yervant ZORIAN
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Publication number: 20230140090Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.Type: ApplicationFiled: October 31, 2022Publication date: May 4, 2023Inventors: Grigor TSHAGHARYAN, Gurgen HARUTYUNYAN, Samvel SHOUKOURIAN, Yervant ZORIAN
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Patent number: 11023310Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.Type: GrantFiled: August 23, 2019Date of Patent: June 1, 2021Assignee: Synopsys, Inc.Inventors: Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Patent number: 10789398Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.Type: GrantFiled: August 23, 2017Date of Patent: September 29, 2020Assignee: Synopsys, Inc.Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Publication number: 20190035484Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Patent number: 10192635Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.Type: GrantFiled: September 28, 2018Date of Patent: January 29, 2019Assignee: Synopsys, Inc.Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Patent number: 10115477Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.Type: GrantFiled: September 28, 2017Date of Patent: October 30, 2018Assignee: Synopsys, Inc.Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Publication number: 20180129769Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.Type: ApplicationFiled: August 23, 2017Publication date: May 10, 2018Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Publication number: 20180130546Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.Type: ApplicationFiled: September 28, 2017Publication date: May 10, 2018Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Patent number: 9831000Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.Type: GrantFiled: September 12, 2014Date of Patent: November 28, 2017Assignee: SYNOPSYS, INC.Inventors: Aram Hakhumyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Patent number: 9514258Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.Type: GrantFiled: June 22, 2012Date of Patent: December 6, 2016Assignee: Synopsys, Inc.Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Determining a desirable number of segments for a multi-segment single error correcting coding scheme
Patent number: 9053050Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.Type: GrantFiled: December 2, 2011Date of Patent: June 9, 2015Assignee: Synopsys, Inc.Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian -
Publication number: 20140380107Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.Type: ApplicationFiled: September 12, 2014Publication date: December 25, 2014Inventors: Aram Hakhumyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Patent number: 8850277Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.Type: GrantFiled: July 15, 2011Date of Patent: September 30, 2014Assignee: Synopsys, Inc.Inventors: Karen Amirkhanyan, Hayk Grigoryan, Gurgen Harutyunyan, Tatevik Melkumyan, Samvel Shoukourian, Alex Shubat, Valery Vardanian, Yervant Zorian
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Publication number: 20130346056Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: SYNOPSYS, INC.Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Publication number: 20130322827Abstract: The invention relates to a connector (CON1, CON2) comprising a first enclosure (ENCL1_CON2P—1, ENCL1_CON1_P2) and at least one electrical contacting means (CE1_ou1, CE1_out—2, CP_out—1, CE1_in—1, CE1_in—2), the first enclosure (ENCL1_CON1_P1, ENCL1_CON1_P2) comprises an inlet (INL) for a first cable (CABLE1) and an outlet (OUTL) for the first cable (CABLE1), the first enclosure (ENCL1_CON1_P1, ENCL1_CON1_P2), the inlet (INL) and the outlet (OUTL) are adapted to completely enclose a first electrical connection between the at least one electrical contacting means (CE1_out—1, CE1_out—2, CP_out—1, CE1_in—1, CE1_in—2) of the connector (CON1, CON2) and at least one conductor (COND_in, COND_out) of the first cable (CABLE1). The invention further relates to an assembly (ASBY1) comprising the connector (CON1, CON2) and the first cable (CABLE1) connected to the connector (CON1, CON2).Type: ApplicationFiled: October 20, 2011Publication date: December 5, 2013Applicant: ALCATEL LUCENTInventors: Karl-Heinz Reimann, Gurgen Harutyunyan, Ekkehard Schomburg, Dietmar Brunsch
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Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme
Publication number: 20130145119Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicant: Synopsys, Inc.Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian -
Publication number: 20130019130Abstract: Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: SYNOPSYS INC.Inventors: Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
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Publication number: 20130019132Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: SYNOPSYS INC.Inventors: Karen AMIRKHANYAN, Hayk Grigoryan, Gurgen Harutyunyan, Tatevik Melkumyan, Samvel Shoukourian, Alex Shubat, Valery Vardanian, Yervant Zorian
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Patent number: 7683744Abstract: A Radio-Frequency (RF) waveguide comprising at least a folded sheet (3) is described, wherein the sheet comprises a first layer made of a plastic, and at least a second layer made of a electric conductive material. Furthermore a method for manufacturing such a RF waveguide plus a device to perform said method is described.Type: GrantFiled: December 14, 2006Date of Patent: March 23, 2010Assignee: Alcatel LucentInventors: Erhard Mahlandt, Olaf Mientkewitz, Gurgen Harutyunyan