Abstract: This disclosure provides systems, methods, and apparatus for implementing a front-end partition of a wireless modems. In one embodiment, a wireless communication apparatus is provided. The wireless communication apparatus includes a wireless local area network modem including a first chip including a first portion of the wireless local area network modem configured to process signals and a second chip including a second portion of the wireless local area network modem. The wireless communication apparatus further includes a wide area network modem. The wireless communication apparatus further includes a combining circuit configured to combine the signals processed by the first portion and a transmission line configured to transmit the combined signals to the second chip and the wide area network modem.

Abstract: Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.

Abstract: A diversity receiver capable of receiving a CDMA system (e.g., a W-CDMA system) and a TDMA system (e.g., a GSM system), with receive diversity for at least one system, is described. W-CDMA is often referred to as UMTS. In one design, the diversity receiver includes a first receiver for GSM and a second receiver for UMTS. The first receiver may be implemented with one receiver design, may be spec-compliant for GSM, and may also support UMTS. The second receiver may be implemented with another receiver design, may be spec-compliant for UMTS, and may also support GSM. The first receiver may include a lowpass filter having a bandwidth that is adjustable for GSM and UMTS. The second receiver may include a bandpass filter used to attenuate a transmit frequency range for UMTS. Each receiver may include circuit blocks that are used for both GSM and UMTS.

Abstract: A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.

Abstract: This disclosure provides systems, methods, and apparatus for implementing a front-end partition of a wireless modems. In one embodiment, a wireless communication apparatus is provided. The wireless communication apparatus includes a wireless local area network modem including a first chip including a first portion of the wireless local area network modem configured to process signals and a second chip including a second portion of the wireless local area network modem. The wireless communication apparatus further includes a wide area network modem. The wireless communication apparatus further includes a combining circuit configured to combine the signals processed by the first portion and a transmission line configured to transmit the combined signals to the second chip and the wide area network modem.

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Abstract: Digital transmitters having improved characteristics are described. In one design of a digital transmitter, a first circuit block receives inphase and quadrature signals, performs conversion from Cartesian to polar coordinates, and generates magnitude and phase signals. A second circuit block (which may include a delta-sigma modulator or a digital filter) generates an envelope signal based on the magnitude signal. A third circuit block generates a phase modulated signal based on the phase signal. The third circuit block may include a phase modulating phase locked loop (PLL), a voltage controlled oscillator (VCO), a saturating buffer, and so on. A fourth circuit block (which may include one or more exclusive-OR gates or an amplifier with multiple gain states) generates a digitally modulated signal based on the envelope signal and the phase modulated signal.

Abstract: A device including a gain control element coupled prior to or within a radio frequency (RF) power amplifier (PA) with an adaptive parametric PA protection circuit is described. In an exemplary embodiment, the device includes a gain control element coupled prior to a radio frequency power amplifier with a power stage with corresponding transistor breakdown threshold values, having an adaptive parametric PA protection circuit configured to receive at least one power stage drain-source voltage parameter value, at least one power stage drain-gate voltage parameter value, and at least one power stage drain-source current parameter value, and including an adaptive parametric PA protection circuit having a first section for processing the parameter values and a second section for generating a gain correction signal to adjust the gain control element with optimal power added efficiency (PAE) for the power stage within the corresponding transistor breakdown threshold values.

Abstract: Techniques for optimizing the power consumption of existing low cost multi-gain state power amplifiers (PA) to increase the talk time of wireless communication devices are described. In an exemplary embodiment a device, such as a baseband processor, operates to set a multistage PA having at least two gain states for amplifying a transmit signal to a lowest power consuming gain state. The device calculates a transition power level as a function of an identified maximum power reduction (MPR) value and switches the PA to a higher gain state from a lower gain state when a transmission power level is higher than the calculated transition power level.

Abstract: Some embodiments provide a method, system, and apparatus for interference cancellation at the baseband of a receiver. A wireless communication device, having a transmitter and receiver, is provided with an adaptive circuit that cancels interference caused by transmit signals (or other signals) leaked or bled onto the receiver at baseband to facilitate detection of a received signal of interest. Some implementations provide for a circuit that approximately reconstructs the second and third order components caused by the nonlinear response of the down-conversion chain of a receiver. This reconstructed signal is then subtracted from the composite received signal to obtain a received signal of interest.

Abstract: A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).

Abstract: A device including a gain control element coupled prior to or within a radio frequency (RF) power amplifier (PA) with an adaptive parametric PA protection circuit is described. In an exemplary embodiment, the device includes a gain control element coupled prior to a radio frequency power amplifier with a power stage with corresponding transistor breakdown threshold values, having an adaptive parametric PA protection circuit configured to receive at least one power stage drain-source voltage parameter value, at least one power stage drain-gate voltage parameter value, and at least one power stage drain-source current parameter value, and including an adaptive parametric PA protection circuit having a first section for processing the parameter values and a second section for generating a gain correction signal to adjust the gain control element with optimal power added efficiency (PAE) for the power stage within the corresponding transistor breakdown threshold values.

Abstract: Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.

Abstract: Techniques for optimizing the power consumption of existing low cost multi-gain state power amplifiers (PA) to increase the talk time of wireless communication devices are described. In an exemplary embodiment a device, such as a baseband processor, operates to set a multistage PA having at least two gain states for amplifying a transmit signal to a lowest power consuming gain state. The device calculates a transition power level as a function of an identified maximum power reduction (MPR) value and switches the PA to a higher gain state from a lower gain state when a transmission power level is higher than the calculated transition power level.

Abstract: A method according to one embodiment includes using a quadrature set of local oscillator signals having duty cycles of substantially less than fifty percent to perform a mixing operation on a radio-frequency current signal. Other embodiments include using a quadrature set of local oscillator signals having duty cycles of less than twenty-five percent.

Abstract: This disclosure describes designs for a digitally controlled oscillator (DCO). The DCO can overcome many of the shortcomings associated with conventional voltage controlled oscillators (VCOs), and may improve wireless communication devices. The described DCO may improve the frequency synthesis process, reduce noise in a wireless communication device, and allow for simplification of various components of the device.

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.