Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Abstract: A computing system having memory components of different tiers. The computing system further includes a processing device, operatively coupled to the memory components, to: receive data access requests; generate a plurality of data access streams in accordance with the data access requests and access characteristics of the request; match characteristics of the data access streams with characteristics of the different tiers of the memory components; and direct the plurality of data access streams to the different tiers of the memory components based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components.

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Abstract: The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.