Patents by Inventor Gurpreet SHINH

Gurpreet SHINH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low-impedance power delivery for a packaged die
    Patent number: 9831225
    Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 28, 2017
    Assignee: NVIDIA Corporation
    Inventors: Gurpreet Shinh, Donald E. Templeton, Brian S. Schieck, Alex Waizman
  • LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE
    Publication number: 20160148915
    Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 26, 2016
    Inventors: Gurpreet SHINH, Donald E. TEMPLETON, Brian S. SCHIECK, Alex WAIZMAN
  • LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE
    Publication number: 20140042637
    Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.
    Type: Application
    Filed: April 10, 2012
    Publication date: February 13, 2014
    Inventors: Gurpreet SHINH, Donald E. TEMPLETON, Brian S. SCHIECK, Alex WAIZMAN