Patents by Inventor Gurpreet Singh

Gurpreet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293913
    Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Gurpreet Singh, Richard E. Schenker, Nityan Labros Nair, Nafees A. Kabir, Gauri Nabar, Eungnak Han, Xuanxuan Chen, Tayseer Mahdi, Brandon Jay Holybee, Charles Henry Wallace, Paul A. Nyhus, Manish Chandhok, Florian Gstrein
  • Patent number: 12286790
    Abstract: A synthetic nonwoven fabric having bonded fibers forming channels surrounding unbonded fibers forming raised slip resistant spots. The fabric is made by extruding hot polymer through a spinneret die onto a moving belt to form a sheet of random fibers, which sheet undergoes a calendering process between a pair of heated rollers, one of which rollers having a plurality of cavities defined in its surface. The resulting fabric can be laminated and otherwise combined with other layers as desired to provide an end product having good slip resistant properties.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: April 29, 2025
    Assignee: BMIC LLC
    Inventor: Gurpreet Singh Sandhar
  • Publication number: 20250126044
    Abstract: Examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. In some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. In some examples, the path of the packet through the multiple routers is based on a topology of the routers.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 17, 2025
    Inventors: Kartik LAKHOTIA, Hossein FARROKHBAKHT, Gurpreet Singh KALSI, Fabrizio PETRINI
  • Patent number: 12277564
    Abstract: A method for detecting duplicate authorization requests includes: receiving an authorization request over an electronic payment processing network associated with an electronic payment transaction; determining whether the authorization request is a potential duplicate authorization request or is not a duplicate authorization request based on a bloom filter; in response to determining that the authorization request is a potential duplicate authorization request, determining a connectivity quality associated with the electronic payment processing network; and determining whether to process the authorization request based on the connectivity quality. A system and computer program product for detecting duplicate authorization requests are also disclosed.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 15, 2025
    Assignee: Visa International Service Association
    Inventor: Gurpreet Singh Bhasin
  • Publication number: 20250119384
    Abstract: Examples described herein relate to a switch or router. In some examples, the switch or router is to: based on receipt of a control packet associated with a first link, store the control packet into a first region of memory associated with the first link; based on receipt of a data packet associated with the first link, store the data packet into a second region of memory associated with the first link; based on the control packet and data packet to egress from a same output port, insert a strict subset of content of the control packet into the data packet to form a second data packet; and cause transmission of the second data packet to a device from the output port.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 10, 2025
    Inventors: Hossein FARROKHBAKHT, Kartik LAKHOTIA, Gurpreet Singh KALSI, Fabrizio PETRINI
  • Patent number: 12267693
    Abstract: Methods and systems provide in-building coverage analytics from mobile measured data. In one embodiment, outlines of buildings in a region are obtained. The outline defines a footprint of the building in the region. The mobile measured data for the region is obtained. The mobile measured data indicates the levels of mobile coverage in the region. The roaming data for the region is obtained. The mobile measured data and the roaming data for each area within each building outline in the region is combined. Buildings having a poor in-building mobile coverage are identified based on the combined mobile measured data and the roaming data.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 1, 2025
    Assignee: T-MOBILE INNOVATIONS LLC
    Inventors: Timothy Indrieri, Gurpreet Singh
  • Patent number: 12266527
    Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Gurpreet Singh, Nityan Labros Nair, Nafees A. Kabir, Eungnak Han, Xuanxuan Chen, Brandon Jay Holybee, Charles Henry Wallace, Paul A. Nyhus, Manish Chandhok, Florian Gstrein, David Nathan Shykind, Thomas Christopher Hoff
  • Publication number: 20250106279
    Abstract: Aspects of the subject disclosure may include, for example, obtaining a graph, applying a first algorithm to the graph to obtain at least one elementary path, applying a rule to each of the at least one elementary path to obtain a respective sanitized elementary path, applying a second algorithm, based on the respective sanitized elementary path, to obtain a respective labeled elementary path, applying a third algorithm to the respective labeled elementary path to identify at least one pattern, mapping a respective pattern of the at least one pattern to a respective graph subsection, applying a fourth algorithm to the respective graph subsection to assign a weight to the respective graph subsection, and allocating a processing of a workload associated with the respective graph subsection to a resource based on the weight. Other embodiments are disclosed.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 27, 2025
    Applicant: CIENA CORPORATION
    Inventors: Pravin Tripathi, Gurpreet Singh, Jatin Sahni
  • Patent number: 12259800
    Abstract: A method for processing data exactly once using transactional stream writes includes receiving, from a client, a batch of data blocks for storage on memory hardware in communication with the data processing hardware. The batch of data blocks is associated with a corresponding sequence number and represents a number of rows of a table stored on the memory hardware. The method also includes partitioning the batch of data blocks into a plurality of sub-batches of data blocks. For each sub-batch of data blocks, the method further includes assigning the sub-batch of data blocks to a buffered stream; writing, using the assigned buffered stream, the sub-batch of data blocks to the memory hardware; updating a storage log with an intent to commit the sub-batch of data blocks using the assigned buffered stream; and committing the sub-batch of data blocks to the memory hardware.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: March 25, 2025
    Assignee: Google LLC
    Inventors: Pavan Edara, Reuven Lax, Ji Yang, Gurpreet Singh Nanda
  • Patent number: 12252576
    Abstract: The present disclosure relates to a process for producing linear alpha olefins in high yield carried out by oligomerization of ethylene in the presence of a novel catalyst composition. The catalyst composition includes Zirconium compound, an organoaluminum compound, and at least one Lewis base selected from cyclic and acyclic ethers (i.e., di-n-butyl ether and diethyl ether). The process for oligomerization of ethylene is carried out in an inert organic solvent in the presence of said catalyst composition. The process as disclosed herein provides significantly high activity of the said catalyst composition resulting in high yield of the alpha olefins (>95 wt. %) as the product and significantly minimum polymer as by-product. The process provides higher yield of C6-C10 fraction with >60 wt. %.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: March 18, 2025
    Assignee: Indian Oil Corporation Limited
    Inventors: Sukhdeep Kaur, Rashmi Rani, Gurmeet Singh, Dheer Singh, Anju Chopra, Gurpreet Singh Kapur, Sankara Sri Venkata Ramakumar
  • Patent number: 12248696
    Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Saurabh Jain, Srivatsa Rangachar Srinivasa, Akshay Krishna Ramanathan, Gurpreet Singh Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney
  • Publication number: 20250071567
    Abstract: Systems and methods for telecommunications network coverage optimization are disclosed. The network coverage optimization system computes a usability index value for a geographic area using measured values of telecommunications network usability indicators. The telecommunications network usability indicators are related to network coverage (e.g., whether the user has enough bars and can make a call), quality of service (e.g., whether the speech and data quality are good), and data speed (e.g., the amount of buffering the user is experiencing). The telecommunications network usability indicators can be selected based on an importance rating associated with them. Then, for each geographic area, the network coverage optimization system computes a score value and a weight value for each selected telecommunications network usability indicator. Using the computed score values and the computed weight values, the network coverage optimization system computes a usability index value for the geographic area.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Gurpreet Singh, Stephen Todd Vancleve
  • Patent number: 12237223
    Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Charles H. Wallace, Manish Chandhok, Mohit K Haran, Gurpreet Singh, Eungnak Han, Florian Gstrein, Richard E. Schenker, David Shykind, Jinnie Aloysius, Sean Pursel
  • Patent number: 12238565
    Abstract: A plurality of access point (AP) devices configured to provide a wireless network at a site within a geographic region and a management system (NMS) configured to manage the plurality of APs are described. An AP device sends, to the NMS, a message including version information of hardware compliance data currently stored at the AP device. The NMS determines, based on the version information, whether the first version of the hardware compliance data stored at the AP device is in compliance with applicable regulations of the geographic region. When the first version is not in compliance, the AP device receives, from the NMS, a second version of the hardware compliance data that is in compliance with the applicable regulations of the geographic region. The AP device enables operation of one or more hardware components of the AP device in accordance with the second version of the hardware compliance data.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 25, 2025
    Assignee: Juniper Networks, Inc.
    Inventors: Joshua Rosenthal, James Jay Friedmann, John James Musante, Gurpreet Singh
  • Publication number: 20250062904
    Abstract: A method, system, and computer program product is provided for third-party authorization. The method includes generating an authorization code, encrypting the authorization code with a public key associated with a first system, resulting in an encrypted authorization code, transmitting the encrypted authorization code to the first system, receiving, from the first system, a digitally signed authorization code generated by the first system based on the authorization code and a private key corresponding to the public key associated with the first system, verifying the digitally signed authorization code based on the public key and the authorization code, and in response to verifying the digitally signed authorization code, transmitting an access token to the first system, wherein the access token is configured to authorize a user with the first system.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Gurpreet Singh Bhasin, Deepak Dhiman, Eric Willard Chamberlain
  • Patent number: 12230536
    Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Florian Gstrein, Eungnak Han, Manish Chandhok, Gurpreet Singh
  • Publication number: 20250054980
    Abstract: This invention relates generally to the field of energy storage, batteries, and cathodes, including cathode materials and methods to make the cathode materials comprising graphene and/or graphene with a plurality of dopants.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 13, 2025
    Applicant: Din Ventures, LLC
    Inventors: Rashed Din, Gurpreet Singh, Sai Aman Gopisetti
  • Publication number: 20250054979
    Abstract: This invention relates generally to the field of energy storage, batteries, cathodes, and anodes. This invention also relates to anode materials and/or cathode materials and methods to make said materials.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 13, 2025
    Applicant: Din Ventures, LLC
    Inventors: Rashed Din, Gurpreet Singh, Sai Aman Gopisetti
  • Patent number: 12200588
    Abstract: In some embodiments, holographically displaying items based on item compatibility with user account features may be facilitated. In some embodiments, first and second mobile devices may be detected as being within a proximity threshold of a holographic display device, where the first mobile device is associated with a first user account and the second mobile device is associated with a second user account. Based on the detection, (i) navigation information of the first and second mobile devices, (ii) return value information indicating respective return values associated with candidate items, and (iii) account feature compatibility information may be obtained and inputted into a machine learning model. Despite a first candidate item being incompatible with a second account feature set for the second mobile device, a first holographic representation of the first candidate item may be displayed.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: January 14, 2025
    Assignee: Capital One Services, LLC
    Inventors: Milan Mehta, Gurpreet Singh Sandhu, Benjamin Polk, Lee Adcock
  • Publication number: 20250004772
    Abstract: Apparatus and method for a decompression hardware copy engine with efficient sequence overlapping copy. For example, one embodiment of an apparatus comprises: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor circuit to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor circuit to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine circuit to execute the copy instructions to produce the decompressed data stream.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Kamlesh PILLAI, Vinodh GOPAL, Gurpreet Singh KALSI, Sreenivas SUBRAMONEY, Wajdi K. FEGHALI