Patents by Inventor Gurtel Sandhu

Gurtel Sandhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6812512
    Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kirk Prall, Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu, Philip J. Ireland
  • Patent number: 6686288
    Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride-coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal that is in contact with the substrate and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: February 3, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kirk Prall, Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu, Philip J. Ireland
  • Publication number: 20010019893
    Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.
    Type: Application
    Filed: April 10, 2001
    Publication date: September 6, 2001
    Inventors: Kirk Prall, Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu, Philip J. Ireland
  • Patent number: 5990021
    Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kirk Prall, Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu, Philip J. Ireland