Patents by Inventor Guru C. Prasad

Guru C. Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit design error detector for electrostatic discharge and latch-up applications
    Patent number: 6493850
    Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 10, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C. S. Raghu, Gopalaro Kadamati
  • Integrated circuit design error detector for electrostatic discharge and latch-up applications
    Publication number: 20020152447
    Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.
    Type: Application
    Filed: February 16, 2001
    Publication date: October 17, 2002
    Inventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C.S. Raghu, Gopalaro Kadamati