Patents by Inventor Guru Prasadh
Guru Prasadh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7395347Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: GrantFiled: August 5, 2003Date of Patent: July 1, 2008Assignee: Newisys, Inc,Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7386626Abstract: Improved techniques are provided for reducing latency in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be encapsulated as inter-cluster packets and stored in a transmission buffer pending transmission on an inter-cluster link. When the transmission buffer is empty, a control character is transmitted on an inter-cluster link. The control character is not stored in the transmission buffer or in a reception buffer, but instead is dropped. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links, including the symbol(s) of the control character.Type: GrantFiled: June 23, 2003Date of Patent: June 10, 2008Assignee: Newisys, Inc.Inventors: Rajesh Kota, Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7281055Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.Type: GrantFiled: May 28, 2002Date of Patent: October 9, 2007Assignee: Newisys, Inc.Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
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Patent number: 7251698Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.Type: GrantFiled: May 28, 2002Date of Patent: July 31, 2007Assignee: Newisys, Inc.Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
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Patent number: 7222262Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.Type: GrantFiled: August 5, 2003Date of Patent: May 22, 2007Assignee: Newisys, Inc.Inventors: Guru Prasadh, David Brian Glasco, Rajesh Kota, Scott Diesing
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Patent number: 7159137Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: GrantFiled: August 5, 2003Date of Patent: January 2, 2007Assignee: Newisys, Inc.Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7155525Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.Type: GrantFiled: May 28, 2002Date of Patent: December 26, 2006Assignee: Newisys, Inc.Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
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Patent number: 7117419Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: GrantFiled: August 5, 2003Date of Patent: October 3, 2006Assignee: Newisys, Inc.Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7103823Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: GrantFiled: August 5, 2003Date of Patent: September 5, 2006Assignee: Newisys, Inc.Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7069392Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency and effectiveness of communications between multiprocessor clusters. Mechanisms for improving the accuracy of information available to an interconnection controller are implemented in order to allow the interconnection controller to increase reliability and reduce latency in a multiple cluster system. Protocol extensions and link layer extensions are provided with packets to convey information between interconnection controllers of separate multiprocessor clusters.Type: GrantFiled: June 12, 2003Date of Patent: June 27, 2006Assignee: Newisys, Inc.Inventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco
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Patent number: 7047372Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.Type: GrantFiled: April 15, 2003Date of Patent: May 16, 2006Assignee: Newisys, Inc.Inventors: Carl Zeitler, David B. Glasco, Rajesh Kota, Guru Prasadh, Richard R. Oehler, David S. Edrich
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Publication number: 20050034033Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: ApplicationFiled: August 5, 2003Publication date: February 10, 2005Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David Glasco
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Publication number: 20050034049Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: ApplicationFiled: August 5, 2003Publication date: February 10, 2005Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David Glasco
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Publication number: 20050034007Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: ApplicationFiled: August 5, 2003Publication date: February 10, 2005Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David Glasco
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Publication number: 20050034048Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.Type: ApplicationFiled: August 5, 2003Publication date: February 10, 2005Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David Glasco
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Publication number: 20050034039Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.Type: ApplicationFiled: August 5, 2003Publication date: February 10, 2005Inventors: Guru Prasadh, David Glasco, Rajesh Kota, Scott Diesing
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Publication number: 20050021699Abstract: According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.Type: ApplicationFiled: June 27, 2003Publication date: January 27, 2005Inventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David Glasco
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Publication number: 20040260832Abstract: Improved techniques are provided for reducing latency in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be encapsulated as inter-cluster packets and stored in a transmission buffer pending transmission on an inter-cluster link. When the transmission buffer is empty, a control character is transmitted on an inter-cluster link. The control character is not stored in the transmission buffer or in a reception buffer, but instead is dropped. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links, including the symbol(s) of the control character.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Applicant: Newisys, Inc., A Delaware corporationInventors: Rajesh Kota, Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco
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Publication number: 20040255002Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency and effectiveness of communications between multiprocessor clusters. Mechanisms for improving the accuracy of information available to an interconnection controller are implemented in order to allow the interconnection controller to increase reliability and reduce latency in a multiple cluster system. Protocol extensions and link layer extensions are provided with packets to convey information between interconnection controllers of separate multiprocessor clusters.Type: ApplicationFiled: June 12, 2003Publication date: December 16, 2004Applicant: Newisys, Inc., A Delaware corporationInventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco
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Publication number: 20040210693Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.Type: ApplicationFiled: April 15, 2003Publication date: October 21, 2004Applicant: Newisys, Inc.Inventors: Carl Zeitler, David B. Glasco, Rajesh Kota, Guru Prasadh, Richard R. Oehler, David S. Edrich