Patents by Inventor Gurunada Thalapaneni

Gurunada Thalapaneni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5238872
    Abstract: The interconnect system of the present invention is comprised of a TiW metal barrier layer as well as a Ti metal barrier layer deposited on the silicon surface. An anisotropic etch process for the Ti/TiW/Al metal sandwich has also been developed without corrosion and metal residue. The addition of the Ti layer between the TiW layer and the silicon surface reduces the contact resistance between the metal and P.sup.+ silicon contact. This Ti layer also effectively improves the blocking of aluminum migration to the silicon surface through TiW grain boundaries. In order to realize good ohmic metal-P.sup.+ contacts, the surface concentration of the silicon should be very high. Therefore, the present invention also employs a plasma mode etch which removes about 250 .ANG. silicon since peak concentrations of P.sup.+ dopants (boron) are often found about 400 .ANG. below the silicon surface. This plasma mode etch will also remove silicon damage caused by previous etching.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: August 24, 1993
    Assignee: Samsung Semiconductor, Inc.
    Inventor: Gurunada Thalapaneni