Patents by Inventor Guruprasad Badakere

Guruprasad Badakere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536690
    Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: September 17, 2013
    Assignee: STATS CHIPPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Patent number: 8153478
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 10, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Patent number: 8120150
    Abstract: An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: February 21, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8072047
    Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: December 6, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20110256670
    Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Patent number: 7989931
    Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Publication number: 20110068448
    Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire.
    Type: Application
    Filed: September 22, 2009
    Publication date: March 24, 2011
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Patent number: 7714419
    Abstract: An integrated circuit package system comprising: providing an elevated tiebar; forming a die paddle connected to the elevated tiebar; attaching an integrated circuit die over the die paddle adjacent the elevated tiebar; attaching a shield over the elevated tiebar and the integrated circuit die; and forming an encapsulant over a portion of the elevated tiebar, the die paddle, and the integrated circuit die.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: May 11, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20090289335
    Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20090166822
    Abstract: An integrated circuit package system comprising: providing an elevated tiebar; forming a die paddle connected to the elevated tiebar; attaching an integrated circuit die over the die paddle adjacent the elevated tiebar; attaching a shield over the elevated tiebar and the integrated circuit die; and forming an encapsulant over a portion of the elevated tiebar, the die paddle, and the integrated circuit die.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 2, 2009
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20090079048
    Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Publication number: 20090072366
    Abstract: An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Guruprasad Badakere Govindaiah, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 6979907
    Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: December 27, 2005
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
  • Publication number: 20050051907
    Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Application
    Filed: October 19, 2004
    Publication date: March 10, 2005
    Applicant: ST Assembly Test Services Ltd.
    Inventors: Jian Li, Il Shim, Guruprasad Badakere
  • Patent number: 6855573
    Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 15, 2005
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
  • Publication number: 20040058477
    Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Application
    Filed: September 19, 2002
    Publication date: March 25, 2004
    Inventors: Jian Jun Li, Il Kwon Shim, Guruprasad Badakere