Abstract: A digital microphone or other sensor assembly includes a transducer and an electrical circuit including a slew-rate controlled output buffer configured to reduce propagation delay and maintain output rise and fall time independent of PVT variation and load capacitance. In some embodiments, the portions of the output buffer are selectably disabled to reduce power consumption without adversely substantially increasing propagation delay.

Abstract: The disclosure relates generally to microphone and vibration sensor assemblies (100) having a transducer (102), like a microelectromechanical systems (MEMS) device, and an electrical circuit (103) disposed in a housing (110) configured for integration with a host device. The electrical circuit includes an output driver circuit, a low drop out (LDO) regulator circuit, and an over-voltage protection circuit with improved capacity and response time.

Abstract: The disclosure relates generally to microphone and vibration sensor assemblies (100) having a transducer (102), like a microelectromechanical systems (MEMS) device, and an electrical circuit (103) disposed in a housing (110) configured for integration with a host device. The electrical circuit includes an output driver circuit, a low drop out (LDO) regulator circuit, and an over-voltage protection circuit with improved capacity and response time.

Abstract: A digital microphone or other sensor assembly includes a transducer and an electrical circuit including a slew-rate controlled output buffer configured to reduce propagation delay and maintain output rise and fall time independent of PVT variation and load capacitance. In some embodiments, the portions of the output buffer are selectably disabled to reduce power consumption without adversely substantially increasing propagation delay.

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Abstract: A digital sensing device includes a sensor diagnostic system for detecting sensor fault conditions. The sensor diagnostic system including an input multiplexer applying a first burnout current or a second burnout current to a selected input channel and a near-rail detector configured to detect when an input voltage of the digital sensing device is near a positive power supply or near a negative power supply. The burnout current injection is applied without interfering with the sensor data. In other embodiments, the sensor diagnostic system may further include an overload detector configured to detect an overflow or underflow condition at the analog-to-digital converter. The sensor diagnostic system may further include a window comparator to detect when the ADC digital output is near a zero digital value. Finally, the sensor diagnostic system may further include a sensor flag generator to generate data flags indicative of sensor fault conditions.

Abstract: A method for calibrating a fixed gain amplifier configured as a front-end amplification stage of an analog-to-digital converter including sampling a calibration voltage with normal and inversed polarity and with the fixed gain amplifier bypassed and with the fixed gain amplifier connected. An actual gain value of the fixed gain amplifier is computed from offset corrected digital output codes generated from converting the calibration voltage. A gain correction value for the fixed gain amplifier can then be computed based on the ratio of the actual gain to the ideal gain. In another embodiment, a method for calibrating an analog-to-digital converter including a fixed gain amplifier, an input buffer and a modulator generates an offset correction value using normal and polarity inversed input samples. The offset correct value provides correction for at least offset errors in the fixed gain amplifier, the input buffer and the modulator.

Abstract: A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second comparators generate respective select signals to turn on only one of the first or the second differential input stage in each amplifier circuit depending on a value of the respective part of the differential input signal. In operation, the first and second complementary differential input stages of each amplifier circuit not being turned on at the same time.

Abstract: A method for calibrating a fixed gain amplifier configured as a front-end amplification stage of an analog-to-digital converter including sampling a calibration voltage with normal and inversed polarity and with the fixed gain amplifier bypassed and with the fixed gain amplifier connected. An actual gain value of the fixed gain amplifier is computed from offset corrected digital output codes generated from converting the calibration voltage. A gain correction value for the fixed gain amplifier can then be computed based on the ratio of the actual gain to the ideal gain. In another embodiment, a method for calibrating an analog-to-digital converter including a fixed gain amplifier, an input buffer and a modulator generates an offset correction value using normal and polarity inversed input samples. The offset correct value provides correction for at least offset errors in the fixed gain amplifier, the input buffer and the modulator.

Abstract: A method for calibrating an analog-to-digital converter includes sampling an analog input signal and generating input samples, reversing the polarity of at least one input sample, averaging the digital output codes associated with a first pair of input samples where the first pair of input samples has opposite polarities, and generating an offset correction value being the average of the digital output codes associated with the first pair of input samples. In another embodiment, a method for calibrating an ADC includes sampling the analog input signal and generating input samples, introducing an incremental value to modify the magnitude of at least one input sample, computing an actual gain value using the digital output codes associated with a first input sample and a second input sample having the modified magnitude, and generating a gain correction value being the ratio of an ideal gain of the ADC to the actual gain.

Abstract: A method for removing component mismatch errors for a system parameter being set by a ratio of two or more physical, electrical components (“components”) of the same kind on an integrated circuit including providing an array of component units having the same component value, determining the actual component values of each component unit in the array, selecting component units based on the actual component values to form pairs of component units where the pairs have approximately the same total component values, ordering the component unit pairs, assigning alternate component unit pairs to be associated with each of the two or more components, rotating at a first frequency the assignment of the component unit pairs. At each rotation, the component unit pairs to be associated with each component are shifted so that each component unit pair is associated with a different one of the two or more components in turn.