Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.

Abstract: An Integrated Circuit (IC) package is provided, comprising a first IC die having a first capacitor and a logic circuit, and a second IC die having a second capacitor. The first IC die and the second IC die may be stacked within the IC package one on top of another and electrically coupled with die-to-die interconnects. The logic circuit is electrically coupled in a power delivery network to the first capacitor and the second capacitor. The first IC die and the second IC die include respective back-end-of-line portions in which the first capacitor and the second capacitor, which may comprise metal-insulator-metal capacitors in some embodiments are situated. In some embodiments, the second capacitor is situated in a shadow of the logic circuit. In various embodiments, the first IC die and the second IC die comprise any suitable pair in a plurality of stacked IC dies within an IC package.

Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.