Abstract: A system for offloading traffic from a cellular network to a broadcast network is provided. The offloading mechanism caters to both unicast and broadcast traffic. The system includes a converged cellular core network, World Wide Web, a CDN, a Broadcast Offload Packet Core (BO-PC), a cellular base station, a Broadcast Radio Head, and a converged UE. The converged cellular core network includes an enhanced packet core, a policy rules engine and a packet inspection and steering unit. The BO-PC includes a Broadcast Proxy, a subscriber database, a Broadcast Offload Service Center, a Broadcast Offload Gateway and an analytics engine. For offloading the unicast traffic, the packet inspection and steering unit identifies sessions that are offloaded for supporting offload of the traffic from the converged cellular core network to the broadcast network.

Abstract: A system for offloading traffic from a cellular network to a broadcast network is provided. The offloading mechanism caters to both unicast and broadcast traffic. The system includes a converged cellular core network, World Wide Web, a CDN, a Broadcast Offload Packet Core (BO-PC), a cellular base station, a Broadcast Radio Head, and a converged UE. The converged cellular core network includes an enhanced packet core, a policy rules engine and a packet inspection and steering unit. The BO-PC includes a Broadcast Proxy, a subscriber database, a Broadcast Offload Service Center, a Broadcast Offload Gateway and an analytics engine. For offloading the unicast traffic, the packet inspection and steering unit identifies sessions that are offloaded for supporting offload of the traffic from the converged cellular core network to the broadcast network.

Abstract: System and method embodiments are disclosed for high availability management for open radio access network (O-RAN). The O-RAN may be deployed on cloud with the O-CU deployed on a region cloud, O-RUs deployed on a cell site O-Cloud, and O-DUs deployed on an edge cloud. Each O-RU may comprise one or more RF clusters, computation clusters, and interface clusters. O-RU instances and O-DU instances may be instantiated with redundancy on the cell site O-Cloud and on the edge cloud, respectively, to serve one or more users. Local and central high-availability (HA) managers may be used to monitor O-RU instance performance for failure prediction/detection and to monitor internal states of each O-DU instance. In response to O-RU instance failure or O-DU internal states beyond/below state thresholds, new O-RU or O-DU instances may be instantiated as replacement instances for O-Cloud high availability management.

Abstract: Described in the present disclosure are system and method embodiments for 5G and WLAN private network convergence to improve Quality of service (QoS) and Quality of experience (QoE) by switching, steering or splitting the traffic using a cognitive layer. The Cognitive layer may sense signal conditions and learn user preferences for traffic allocation between available Wi-Fi and 5G networks. In embodiments, the cognitive layer may comprise an Artificial Intelligence (AI) or Machine Learning (ML) module, signal conditions sensor, and user QoS/QoE aware schedulers. A cloud-based service controller may be incorporated to make decisions on user QoS and QoE allocation based on the cognitive layer input. Implementation of the network convergence embodiments may improve QoS/QoE.

Abstract: System and method embodiments are disclosed to improve radio access network coverage area, increase throughput, and reduce power consumption in user equipment (UE). Downlink (DL) and uplink (UL) are disaggregated in one or more radio units (RUs). A UE receives DL data packets from a DL RU and uploads UL data packets to a UL RU disaggregated from the DL RU. The UL RU couples to a distributed unit (DU) directly or via the DL RU such that an acknowledgment or error message for successful or unsuccessful reception of the UL data packets may be sent back to the UE via the DL RU. The DU may track a UE motion trajectory and re-map UL traffic from one UL RU to another UL RU. Embodiments of DL/UL disaggregation may improve power efficiency and be advantageous for various applications such as internet of things, cyber physical systems, 5G communications, etc.

Abstract: A system for improving indoor coverage of cellular reception is provided. The system includes an Intelligent receiver and a Pico transmitter. The intelligent receiver demodulates a signal received from a Broadcast radio head (BRH) with a HPHT or a LPLT toplogy through an outdoor high gain rooftop antenna that is externally connected to the intelligent receiver. The intelligent receiver includes an artificial intelligence (AI) or Machine learning (ML) based indoor coverage monitoring unit and a Pico transmitter application. The AI/ML based indoor coverage monitoring unit continuously monitors cellular reception factors of indoor user devices. The AI/ML based indoor coverage monitoring unit predicts an optimal indoor modulation profile and selects a required modulation index required for the indoor user devices. The Pico transmitter application re-broadcasts or relays the demodulated signal, based on an optimal indoor modulation profile required for the indoor user devices.

Abstract: A system for improving indoor coverage of cellular reception is provided. The system includes an Intelligent receiver and a Pico transmitter. The intelligent receiver demodulates a signal received from a Broadcast radio head (BRH) with a HPHT or a LPLT toplogy through an outdoor high gain rooftop antenna that is externally connected to the intelligent receiver. The intelligent receiver includes an artificial intelligence (AI) or Machine learning (ML) based indoor coverage monitoring unit and a Pico transmitter application. The AI/ML based indoor coverage monitoring unit continuously monitors cellular reception factors of indoor user devices. The AI/ML based indoor coverage monitoring unit predicts an optimal indoor modulation profile and selects a required modulation index required for the indoor user devices. The Pico transmitter application re-broadcasts or relays the demodulated signal, based on an optimal indoor modulation profile required for the indoor user devices.

Abstract: Disclosed is a system and method for establishing a device to device communication link in cellular networks. The system includes one or more user equipments, and a base station. The one or more user equipments includes a first user equipment and a second user equipment. The first user equipment is configured with a first user equipment cognitive engine and the second user equipment is configured with a second user equipment engine. The base station that is coupled to a cellular tower and configured with an evolved packet core EPC. The base station and at least one of the one or more user equipments performs a method for establishing the device to device communication link in the cellular network using a transmit to receive transition gap (TTG) and a receive to transmit transition gap (RTG).

Abstract: Disclosed is a system and method for establishing a device to device communication link in cellular networks. The system includes one or more user equipments, and a base station. The one or more user equipments includes a first user equipment and a second user equipment. The first user equipment is configured with a first user equipment cognitive engine and the second user equipment is configured with a second user equipment engine. The base station that is coupled to a cellular tower and configured with an evolved packet core EPC. The base station and at least one of the one or more user equipments performs a method for establishing the device to device communication link in the cellular network using a transmit to receive transition gap (TTG) and a receive to transmit transition gap (RTG).

Abstract: A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.

Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.