Abstract: An apparatus and method for unaligned cache reads is implemented. Data signals on a system bus are remapped into a cache line wherein a plurality of data values to be read from the cache are output in a group-wise fashion. The remapping defines a grouping of the data values in the cache line. A multiplexer is coupled to each group of storage units containing the data values, wherein a multiplexer input is coupled to each storage unit in the corresponding group. A logic array coupled to each MUX generates a control signal for selecting the data value output from each MUX. The control signal is generated in response to the read address which is decoded by each logic array.

Abstract: A first clock stage in a circuit utilizes a second stage clock for triggering the falling edge of a first clock stage output. The output will not reset until both the first clock is low and the second clock are high due to the addition of the second clock signal. This is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal. The clock signal is inverted by an inverter connected to the gate of the additional P-FET. Stability is provided to the first stage by creating a full keeper, which holds the output from the logic device in the first stage. A pair of transistors are connected by their drains to the output of the logic device. The transistors are controlled by an inverter, which is connected to the pairs' bases, wherein the inverter receives the output from the logic device.

Abstract: As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.

Abstract: A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way that additional lines are not required, and so that substantially the same circuitry may be used for either single-ended mode or differential mode. Further, a selectable-mode driver may be connected to a non-selectable mode receiver, and vice versa. The invention may be implemented as a selectable driver, a selectable receiver, or a selectable driver/receiver pair. The apparatus and method of the present invention apply to both uni-directional and bi-directional bus implementations. The invention uses the same bus lines (i.e. wires) and substantially the same circuitry for both single-ended and differential modes of operation. When operating in single-ended mode, the data width of the bus is twice the data width as when operating in differential mode.

Abstract: A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.

Abstract: A comparator circuit (40) includes a comparator network and a comparator enabling device (80) and may be integrated with a sense amplifier circuit (41). The comparator network is adapted to receive a complementary pair of reference data signals (B, B13) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (40) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (80) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Abstract: The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.

Abstract: A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines).

Abstract: A memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.

Abstract: A novel SRAM construction allows for reduced power consumption by conditionally restoring only these memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines).

Abstract: A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock).

Abstract: A set associative cache memory array includes redundant memory portions for use in the case of a defective portion of the memory. Information is stored within the defective portion of the memory array and an identical copy is stored within the redundant portion. Additionally, reading of the information is done from both the defective portion and the redundant portion. Selection of the information from either the defective portion or the redundant portion is made using programmable circuitry such as a fuse.

Abstract: A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.

Abstract: A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.

Abstract: An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.