Abstract: An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry 18 generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path 26 to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory 4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.

Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.

Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.

Abstract: An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry 18 generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path 26 to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory 4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.

Abstract: A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34. An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback signal generated in response to the input signal within the first power domain containing the first buffer circuit 30 is passed directly to the second buffer circuit 32, 34 to control the output signal level reaching the other of the output values. A feedback circuit comprising cross-coupled PMOS transistors 38, 40 is provided to boost the feedback signal level up to the voltage level of the second voltage domain which contains the feedback circuit 38, 40 as well as the second buffer circuit 32, 34. The level shifter circuit 28 has a low latency and a low static power consumption.

Abstract: A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34. An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback signal generated in response to the input signal within the first power domain containing the first buffer circuit 30 is passed directly to the second buffer circuit 32, 34 to control the output signal level reaching the other of the output values. A feedback circuit comprising cross-coupled PMOS transistors 38, 40 is provided to boost the feedback signal level up to the voltage level of the second voltage domain which contains the feedback circuit 38, 40 as well as the second buffer circuit 32, 34. The level shifter circuit 28 has a low latency and a low static power consumption.

Abstract: A zero-write-cycle memory cell apparatus for simultaneously reading and writing data to and from a memory cell via isolated read and write wordlines wherein read cycles operate without dedicated write cycles. The zero-write-cycle memory cell apparatus includes a memory cell or storage circuit for the storage of binary data and a write circuit for writing binary data to the memory cell or storage circuit wherein the write circuit includes a write wordline. The presence of a binary data signal at the write wordline optimizes write performance independently of a read path from the memory cell. The zero-write-cycle memory cell apparatus further includes a read circuit for reading binary data from the memory cell or storage circuit. The read circuit includes a read wordline. The presence of a binary data signal at the read wordline optimizes read performance independently of a write path into said memory cell.

Abstract: Referring to FIGS. 1, 4, and 5, I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow the transfer of pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29). In one embodiment, a pins/status bus (e.g. 76) may be programmably configured to permit the logical combination of the outputs of multiple channels (e.g. 160, 161, 185) in order to determine the logic state of an output pin (165). In one embodiment, the output event bus portion (e.g. 132) of a pin/status bus (e.g. 76) includes one or more set conductors (137), one or more clear conductors (138), and one or more toggle conductors (139), which may be wire-NOR conductors.