Abstract: A temperature controller (1) for a temperature control mechanism (M) arranged for heating of a device (2) is described. The temperature controller (1), includes an input (3) for a temperature signal (Y), an output (4) for a control signal U for controlling the temperature controller, and a first control loop mechanism (CLM1) can output a first predicted temperature ({tilde over (X)}) of the gas surrounding the device. The temperature controller also includes a first model ({tilde over (S)}) of the thermal properties of the device, a second model ({tilde over (M)}) of the thermal properties of the device, and a second control loop mechanism (CLM2) can output the control signal (U).

Abstract: A temperature controller (1) for a temperature control mechanism (M) arranged for heating of a device (2) is described. The temperature controller (1), comprises an input (3) for a temperature signal (Y), an output (4) for a control signal U for controlling the temperature controller, and a first control loop mechanism (CLM1) configured to output a first predicted temperature (X) of the gas surrounding the device. The temperature controller also comprises a first model (S) of the thermal properties of the device, a second model (M) of the thermal properties of the device, and a second control loop mechanism (CLM2) configured to output the control signal (U).

Abstract: There is disclosed integrated circuitry having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.

Abstract: There is disclosed integrated circuitry comprising having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also comprises has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.